SILICON-BASED SEMICONDUCTOR DEVICE COMPRISING eFUSES FORMED BY AN EMBEDDED SEMICONDUCTOR ALLOY

• US 20110156857A1
• Filed: 10/15/2010
• Published: 06/30/2011
• Est. Priority Date: 12/29/2009
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kronholz, Stephan, Boschke, Roman, Kurz, Andreas
• Application Number:
  US12/905,779
• Publication Number:
  US 20110156857A1
• Time in Patent Office: Days
• US Class Current: 337/414
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/49107 Fuse making

Abstract

An electronic fuse may receive a silicon/germanium material in the fuse body, which in turn may result in the formation of a metal silicide material of reduced thickness. Consequently, the current density and, thus, the electromigration and heat generation in the metal silicide material may be increased for a given amount of current. Consequently, transistor switches for applying the programming pulse to the electronic fuse may be reduced in size.

Claims

1. A method of forming an electronic fuse of a semiconductor device, the method comprising:

forming an isolation structure in a semiconductor layer so as to laterally delineate a fuse region in said semiconductor layer; and

forming a metal silicide material in said fuse region, said metal silicide material having a first thickness in a contact area of said electronic fuse and having a second thickness in a fuse body of said electronic fuse, said second thickness being less than said first thickness.

2. The method of claim 1, further comprising replacing material of said semiconductor layer, at least in a portion of said fuse body, with a semiconductor material having a reduced silicidation rate relative to said replaced material.

3. The method of claim 2, wherein replacing material of said semiconductor layer, at least in a portion of said fuse body, comprises forming a cavity in said fuse body and regrowing a semiconductor alloy in said cavity.

4. The method of claim 3, wherein said semiconductor alloy is a strain-inducing semiconductor alloy used to replace a portion of active regions of transistors formed in and above said semiconductor layer.

5. The method of claim 3, wherein said semiconductor alloy comprises a crystalline silicon/germanium mixture.

6. The method of claim 1, further comprising incorporating a diffusion blocking species into said fuse body prior to forming said metal silicide material, wherein said diffusion blocking species reduces an interdiffusion of metal and silicon when forming said metal silicide.

7. The method of claim 6, wherein said diffusion blocking species comprises at least one of oxygen and nitrogen.

8. A method of forming an electronic fuse of a semiconductor device, the method comprising:

replacing at least a portion of a semiconductor material of a fuse region with a semiconductor mixture, said semiconductor mixture having a silicidation rate that is less than a silicidation rate of said at least a portion;

forming a metal silicide material in said semiconductor mixture; and

forming contact elements in an interlayer dielectric material so as to connect to contact areas formed in said fuse region.

9. The method of claim 8, wherein replacing at least a portion of a semiconductor material of a fuse region comprises laterally delineating a body region and a first and second contact area in said fuse region and selectively replacing at least a part of said body region with said semiconductor mixture.

10. The method of claim 8, wherein replacing at least a portion of a semiconductor material of a fuse region comprises laterally delineating a body region and a first and second contact area in said fuse region and replacing at least a part of said body region and said first and second contact areas with said semiconductor mixture.

11. The method of claim 8, wherein replacing at least a portion of a semiconductor material of a fuse region comprises forming a cavity in said fuse region so as to preserve said semiconductor material at a bottom of said cavity and refilling said cavity with said semiconductor mixture.

12. The method of claim 8, further comprising forming a transistor in and above a semiconductor region and incorporating said semiconductor mixture into a part of said semiconductor region.

13. The method of claim 12, wherein said semiconductor mixture is formed in said fuse region and in said semiconductor region in a common process sequence.

14. The method of claim 8, wherein said semiconductor mixture comprises a silicon/germanium alloy.

15. The method of claim 8, wherein replacing at least a portion of a semiconductor material of a fuse region with a semiconductor mixture comprises incorporating an implantation species into said at least a portion so as to provide said semiconductor mixture as a compound of said semiconductor material and said implantation species.

16. A semiconductor device, comprising:

a circuit element formed in and above a first semiconductor region of a semiconductor layer; and

an electronic fuse formed in a second semiconductor region of said semiconductor layer, said electronic fuse comprising a first contact area, a second contact area and a fuse body formed in said second semiconductor region, at least said fuse body comprising a first silicon-containing material having a first silicidation rate with respect to a predefined silicidation recipe, said fuse body further comprising a second silicon-containing material formed above said first silicon-containing material and having a second silicidation rate that is less than said first silicidation rate, said electronic fuse further comprising a metal silicide formed in said first and second contact areas and said fuse body according to said predefined silicidation recipe.

17. The semiconductor device of claim 16, wherein a thickness of said metal silicide formed in said fuse body is less than the thickness of said metal silicide formed in said first and second contact areas.

18. The semiconductor device of claim 16, wherein said second semiconductor region is formed on a buried insulating material.

19. The semiconductor device of claim 16, wherein at least said fuse body comprises a crystalline silicon/germanium mixture.

20. The semiconductor device of claim 16, wherein a lateral dimension of said first and second contact regions along a direction perpendicular to a current flow direction in said fuse body is greater than a corresponding lateral dimension of said fuse body.