DATA OUTPUT CIRCUIT

• US 20110156938A1
• Filed: 07/09/2010
• Published: 06/30/2011
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Dong Uk
• Granted Patent: US 8,212,694 B2
• Time in Patent Office: Days
• US Class Current: 341/101
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A data output circuit is presented. The data output circuit includes: a data serializer and a driver. The data serializer is configured to generate serial data using first parallel data. The driver is configured to drive the serial data to generate output data. The data serializer is also configured to generate the serial data by multiplexing second parallel data generated by changing a power domain of the first parallel data.

Claims

1. A data output circuit comprising:

a data serializer configured to generate serial data using first parallel data; and

a driver configured to drive the serial data to generate output data,

wherein the data serializer is configured to generate the serial data by multiplexing second parallel data generated by changing a to power domain of the first parallel data.

2. The data output circuit according to claim 1, wherein the data serializer comprises:

a data level shifter configured to shift a voltage level of the first parallel data to generate level shifted data; and

a multiplexing section configured to multiplex the level shifted data in response to clock signals, and generate the serial data.

3. The data output circuit according to claim 2, wherein the multiplexing section has a different power domain from that of the driver.

4. The data output circuit according to claim 2, wherein the data level shifter has the same power domain as that of the driver.

5. A data output circuit comprising:

a power domain changing unit configured to change power domains of a plurality of first clock signals to generate a plurality of second clock signals; and

an output unit configured to selectively output a plurality of level shifted data generated by shifting voltage levels of a plurality of data, in response to the plurality of second clock signals.

6. The data output circuit according to claim 5, further to comprising a repeater configured to receive the plurality of second clock signals to transfer the plurality of second clock signals to the output unit.

7. The data output circuit according to claim 5, further comprising an output control unit configured to receive a plurality of data clock signals that correspond to an activation interval of an output enable signal and to output the plurality of first clock signals to the power domain changing unit.

8. The data output circuit according to claim 5, wherein the output unit comprises:

a data serializer configured to multiplex the plurality of data in response to the plurality of second clock signals, and to generate serial data; and

a driver configured to drive the serial data to generate output data.

9. The data output circuit according to claim 8, wherein the data serializer comprises:

a data level shifter configured to shift the voltage levels of the plurality of data to generate the plurality of level shifted data; and

a multiplexing section configured to multiplex the plurality of level shifted data in response to the plurality of second clock signals, and to generate the serial data.

10. The data output circuit according to claim 9, wherein the multiplexing section has a different power domain from that of the driver.

11. The data output circuit according to claim 9, wherein the data level shifter has the same power domain as that of the driver.

12. A data output circuit comprising:

a power domain changing unit configured to change power domains of a plurality of first clock signals having multi-phases and to generate a plurality of second clock signals having multi-phases;

a plurality of output units configured to commonly receive the plurality of second clock signals and respectively receive a plurality of first data sets; and

a plurality of repeaters configured to transfer the plurality of second clock signals to the plurality of output units,

wherein each output unit is configured to selectively output a second data set generated by changing a power domain of the respectively received first data set, in response to the commonly s received second clock signals.

13. The data output circuit according to claim 12, wherein each of the output units comprises:

a data serializer configured to multiplex the respectively to received first data set in response to the commonly received second clock signals, and to generate the second data set; and

a driver configured to drive the second data set to generate output data.

14. The data output circuit according to claim 13, wherein the data serializer comprises:

a data level shifter configured to shift a voltage level of the respectively received first data set to generate the second data set; and

a multiplexing section configured to multiplex the second data set in response to the commonly received second clock signals, and to generate serial data.

15. The data output circuit according to claim 14, wherein the multiplexing section has a different power domain from that of the driver.

16. The data output circuit according to claim 14, wherein the data level shifter has the same power domain as that of the driver.