Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design

• US 20110157982A1
• Filed: 07/02/2010
• Published: 06/30/2011
• Est. Priority Date: 07/10/2009
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Hsu, Fu-Chang
• Granted Patent: US 8,233,320 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

Claims

1. A NAND-based 2T-NOR flash memory array comprising:

a plurality of NAND-based 2T-NOR flash cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each of said NAND-based 2T-NOR flash cells having a storage transistor with a cell gate, a source and a drain, and an access transistor with a select gate, a source and a drain, said source of said access transistor being connected in series with said drain of said storage transistor;

a plurality of word lines with each word line connecting the cell gates of a row of said 2T-NOR flash cells, said word lines running in an X direction;

a plurality of select-gate lines with each select-gate line connecting the select gates of a row of said 2T-NOR flash cells;

a plurality of source lines with each source line connecting the sources of the storage transistors of one and only one column of said 2T-NOR flash cells, said source lines running in a Y direction perpendicular to said word lines;

a plurality of bit lines with each bit line connecting the drains of the access transistors of one and only one column of said 2T-NOR flash cells, said bit lines running in parallel with said source lines; and

wherein said NAND-based 2T-NOR flash memory array is partitioned into a plurality of memory sectors, each memory sector having a plurality of memory blocks, each memory block having a plurality of memory pages, and each memory page having one row of said NAND-based 2T-NOR flash cells with one word line and one select-gate line.

2. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page pre-program operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with 20V, and all other word lines, all source lines, all bit lines and all select-gate lines in said flash memory array are applied with 0V.

3. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page pre-program verify operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with a threshold voltage Vt of the 2T-NOR flash cells, the select-gate line of said selected memory page is applied with a power supply voltage Vdd, all bit lines in said selected memory sector are pre-charged to Vdd−

Vt, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.

4. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a block pre-program operation of a selected memory block in a selected memory sector, the word lines of said selected memory block are applied with 20V, and all other word lines, all source lines, all bit lines and all select-gate lines in said flash memory array are applied with 0V.

5. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a block pre-program verify operation of a selected memory block in a selected memory sector, the word lines of said selected memory block are applied with a threshold voltage Vt of the 2T-NOR flash cells, the select-gate lines of said selected memory block are applied with a power supply voltage Vdd, all bit lines in said selected memory sector are pre-charged to Vdd−

Vt, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.

6. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a sector pre-program operation of a selected memory sector, all word lines of said selected memory sector are applied with 20V, and all other word lines, all source lines, all bit lines and all select-gate lines in said flash memory array are applied with 0V.

7. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a sector pre-program verify operation of a selected memory sector, all word lines of said selected memory sector are applied with a threshold voltage Vt of the 2T-NOR flash cells, all select-gate lines of said selected memory sector are applied with a power supply voltage Vdd, all bit lines in said selected memory sector are pre-charged to Vdd−

Vt, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.

8. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a chip pre-program operation of said flash memory array, all word lines in said flash memory array are applied with 20V, and all source lines, all bit lines and all select-gate lines in said flash memory array are applied with 0V.

9. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a chip pre-program verify operation of said flash memory array, all word lines in said memory array are applied with a threshold voltage Vt of the 2T-NOR flash cells, all select-gate lines in said flash memory array are applied with a power supply voltage Vdd, all bit lines in said flash memory array are pre-charged to Vdd−

Vt, and all source lines in said flash memory array are applied with 0V.

10. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page erase operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with 0V, all other word lines and all select-gate lines in said selected memory sector are coupled to 20V, all bit lines and all source lines in said selected memory sector are forwarded with 20V which is applied to triple P-wells of the 2T-NOR flash cells in said selected memory sector, and all word lines, all source lines, all bit lines and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

11. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page erase verify operation of a selected memory page in a selected memory block of a selected memory sector, the select-gate line of said selected memory page is applied with a power supply voltage Vdd, all source lines in said selected memory sector are applied with 1V, all bit lines in said selected memory sector are pre-discharged to 0V, and all word lines, all other select-gate lines, all other bit lines and all other source lines in said flash memory array are applied with 0V.

12. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a block erase operation of a selected memory block in a selected memory sector, the word lines of said selected memory block are applied with 0V, all other word lines and all select-gate lines in said selected memory sector are coupled to 20V, all bit lines and all source lines in said selected memory sector are forwarded with 20V which is applied to triple P-wells of the 2T-NOR flash cells in said selected memory sector, and all word lines, all source lines, all bit lines and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

13. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a sector erase operation of a selected memory sector, all word lines of said selected memory sector are applied with 0V, all select-gate lines in said selected memory sector are coupled to 20V, all bit lines and all source lines in said selected memory sector are forwarded with 20V which is applied to triple P-wells of the 2T-NOR flash cells in said selected memory sector, and all word lines, all source lines, all bit lines and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

14. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a chip erase operation of said flash memory array, all word lines in said flash memory array are applied with 0V, all select-gate lines in said flash memory array are coupled to 20V, all bit lines and all source lines in said flash memory array are forwarded with 20V which is applied to triple P-wells of the 2T-NOR flash cells in said flash memory array.

15. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page program operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with a voltage in a range between 15V and 20V, all other word lines and all select-gate lines in said selected memory sector are applied with 5V, the bit lines and the source lines of program data in said selected memory sector are applied with 0V, the bit lines and the source lines of program-inhibit data in said selected memory sector are applied with approximately 8V, and all other word lines, all other source lines, all other bit lines and all other select-gate lines in said flash memory array are applied with 0V.

16. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a page program verify operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with a threshold voltage Vt of the 2T-NOR flash cells, the select-gate line of said selected memory page is applied with a power supply voltage Vdd, all bit lines in said selected memory sector are pre-charged to Vdd−

Vt, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.

17. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, all word lines in said selected memory sector are applied with a power supply voltage Vdd or a boost voltage Vboost, the select-gate line in said selected memory page is applied with Vboost, all bit lines in said selected memory sector is applied with 1V, and all other word lines, all other select-gate lines, all other bit lines and all source lines in said flash memory array are applied with 0V.

18. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein erase and program operations of each of said 2T-NOR flash cells are based on a Fowler-Nordheim channel tunneling process with no voltage difference between the drain and the source of said storage transistor.

19. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein said storage and access transistors of each of said 2T-NOR flash cells are NAND-based double-poly transistors each having a floating gate, said cell gate and said select gate are poly2 gates, and the two floating gates are made of a poly1 layer underneath the two poly2 gates.

20. The NAND-based 2T-NOR flash memory array as claimed in claim 19, wherein each of said 2T-NOR flash cells is a single-level cell, said access transistor has a threshold voltage substantially centered at 0.75V in a range between 0.5V and 1V, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

21. The NAND-based 2T-NOR flash memory array as claimed in claim 19, wherein each of said 2T-NOR flash cells is a multi-level cell, said access transistor has a threshold voltage substantially centered at 0.75V in a range between 0.5V and 1V, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.

22. The NAND-based 2T-NOR flash memory array as claimed in claim 19, wherein the floating gate and said select gate of said access transistor are shorted together.

23. The NAND-based 2T-NOR flash memory array as claimed in claim 22, wherein each of said 2T-NOR flash cells is a single-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 layer, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

24. The NAND-based 2T-NOR flash memory array as claimed in claim 22, wherein said 2T-NOR flash cell is a multi-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 layer, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.

25. The NAND-based 2T-NOR flash memory array as claimed in claim 1, wherein said storage transistor of each of said 2T-NOR flash cells is a NAND-based double-poly transistor with said cell gate being a poly2 gate and a floating gate made of a poly1 layer underneath said poly2 gate, and said access transistor of each of said 2T-NOR flash cells is a single-poly poly1 or poly2 NMOS transistor with said select gate being a poly1 or poly2 gate.

26. The NAND-based 2T-NOR flash memory array as claimed in claim 25, wherein each of said 2T-NOR flash cells is a single-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 or poly2 NMOS transistor, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

27. The NAND-based 2T-NOR flash memory array as claimed in claim 25, wherein each of said 2T-NOR flash cells is a multi-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 or poly2 NMOS transistor, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.

28. The NAND-based 2T-NOR flash memory array as claimed in claim 1, further comprising:

a plurality of global bit lines with each global bit line connecting through an odd bit-line gate to the bit line of an odd column of said 2T-NOR flash cells and an even bit-line gate to the bit line of an even column of said 2T-NOR flash cells immediately following said odd column; and

a plurality of global source lines with each global source line connecting through an odd source-line gate to the source line of said odd column of said 2T-NOR flash cells and an even source-line gate to the source line of said even column of said 2T-NOR flash cells immediately following said odd column.

29. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during a pre-program operation, all source-line gates and all bit-line gates of a selected memory sector are applied with a power supply voltage Vdd so that the source lines and the bit lines in said selected memory sector are passed with voltages applied to the global source lines and the global bit lines in said selected memory sector respectively, and all source-line gates and all bit-line gates of all other memory sectors in said flash memory array are applied with 0V.

30. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during an erase operation, all source-line gates and all bit-line gates of a selected memory sector are applied with a power supply voltage Vdd so that the source lines and the bit lines in said selected memory sector are passed with voltages applied to the global source lines and the global bit lines in said selected memory sector respectively, and all source-line gates and all bit-line gates of all other memory sectors in said flash memory array are applied with 0V.

31. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during a page erase verify operation of a selected memory page in a selected memory block of a selected memory sector, the select-gate line of said selected memory page is applied with a power supply voltage Vdd, all source-line gates and all bit-line gates of said selected memory page are applied with Vdd, all global source lines in said selected memory sector are applied with 1V, all global bit lines in said selected memory sector are pre-discharged to 0V, and all word lines, all other select-gate lines, all other global bit lines, all other global source lines, all other bit-line gates and all other source-line gates in said flash memory array are applied with 0V.

32. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during a page program operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with a voltage in a range between 15V and 20V, all other word lines and all select-gate lines in said selected memory sector are applied with 5V, all source-line gates and all bit-line gates of said selected memory page are applied with 10V, the global bit lines and the global source lines of program data in said selected memory sector are applied with 0V, the global bit lines and the global source lines of program-inhibit data in said selected memory sector are applied with approximately 8V, and all other word lines, all other global source lines, all other global bit lines, all other bit-line gates, all other source-line gates and all other select-gate lines in said flash memory array are applied with 0V.

33. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during a page program verify operation of a selected memory page in a selected memory block of a selected memory sector, the word line of said selected memory page is applied with a threshold voltage Vt of the 2T-NOR flash cells, the select-gate line of said selected memory page is applied with a power supply voltage Vdd, all source-line gates and all bit-line gates of said selected memory page are applied with Vdd, all global bit lines in said selected memory sector are pre-charged to Vdd−

Vt, and all other word lines, all other select-gate lines, all other global bit lines, all other bit-line gates, all other source-line gates and all global source lines in said flash memory array are applied with 0V.

34. The NAND-based 2T-NOR flash memory array as claimed in claim 28, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, all word lines in said selected memory sector are applied with a power supply voltage Vdd or a boost voltage Vboost, the select-gate line in said selected memory page is applied with Vboost, all global bit lines in said selected memory sector is applied with 1V, all source-line gates and all bit-line gates of said selected memory page are applied with Vdd, and all other word lines, all other select-gate lines, all other global bit lines and all global source lines in said flash memory array are applied with 0V.

35. A NAND-based 2T-NOR flash memory device comprising:

a NAND-based 2T-NOR flash memory array having a plurality of memory sectors, each memory sector having a plurality of memory blocks, each memory blocks having a plurality of memory pages, and each memory page having one row of NAND-based 2T-NOR flash cells with one word line and one select-gate line;

a write-row-decoder coupled to the word lines of said flash memory array;

a read-row-decoder coupled to the select-gate lines of said flash memory array;

a data buffer and slow speed page sense amplifier unit connected to a plurality of bit lines of said flash memory array, said data buffer and slow speed page sense amplifier unit having slow speed page sense amplifiers and a data buffer for storing program;

a Y-pass gate and Y-decoder unit having Y-pass gates and Y-decoders;

a byte/word high speed sense amplifier unit connected to said Y-pass gate and Y-decoder unit, said byte/word high speed sense amplifier unit having high speed sense amplifiers; and

an isolate device unit coupling said Y-pass gate and Y-decoder unit to said bit lines of said flash memory array.

36. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said slow speed page sense amplifiers, said high speed sense amplifiers, said Y-pass gates and said Y-decoders are made of low voltage devices.

37. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said slow speed page sense amplifiers are used to perform precise threshold voltage verification for pre-program, erase and program operations in a slow speed, low current and page sensing scheme.

38. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said isolate device unit is turned on as a sensing path to said bit lines, said Y-pass gates are decoded by said Y-decoders to connect said byte/word high speed sense amplifier unit to said bit lines, and said data buffer and slow speed page sense amplifier unit is disconnected from said bit lines in a high speed sensing scheme.

39. The NAND-based 2T-NOR flash memory device as claimed in claim 38, wherein said isolate device unit has a gate voltage tied to a boost voltage Vboost to turn on said isolate device unit as a sensing path when a read operation is performed in said high speed sensing scheme.

40. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a page pre-program operation of a selected memory page in a selected memory block of a selected memory sector, said write-row-decoder connects 20V to the word line of said selected memory page, and 0V to all other word lines in said flash memory array.

41. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a block pre-program operation of a selected memory block in a selected memory sector, said write-row-decoder connects 20V to the word lines of said selected memory block, and 0V all other word lines in said flash memory array.

42. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a sector pre-program operation of a selected memory sector, said write-row-decoder connects 20V to all word lines of said selected memory sector, 0V to all other word lines in said flash memory array.

43. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said write-row-decoder is further coupled to the select-gate lines of said flash memory array, and during a pre-program operation of said flash memory array, said read-row-decoder is decoupled from all select-gate lines, and said write-row-decoder connects 20V to all select-gate lines in said flash memory array.

44. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a page erase operation of a selected memory page in a selected memory block of a selected memory sector, said write-row-decoder connects 0V to the word line of said selected memory page, all other word lines in said selected memory sector are coupled to 20V, and all word lines of all other memory sectors in said flash memory array are applied with 0V.

45. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a block erase operation of a selected memory block in a selected memory sector, said write-row-decoder connects 0V to the word lines of said selected memory block, all other word lines in said selected memory sector are coupled to 20V, and all word lines of all other memory sectors in said flash memory array are applied with 0V.

46. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a sector or chip erase operation, said write-row-decoder connects 0V to all word lines of all memory sectors in said flash memory array.

47. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said write-row-decoder is further coupled to the select-gate lines of said flash memory array, and during a page program operation of said flash memory array, said read-row-decoder is decoupled from all select-gate lines of said flash memory array, and said write-row-decoder connects a voltage in a range between 15V and 20V to one of select-gate lines in said flash memory array.

48. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said write-row-decoder is further coupled to the select-gate lines of said flash memory array, and during a chip erase operation of said flash memory array, said read-row-decoder is decoupled from all select-gate lines and said write-row-decoder connects 0V to all select-gate lines of all memory sectors in said flash memory array.

49. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a page program operation of a selected memory page in a selected memory block of a selected memory sector, said write-row-decoder connects a voltage in a range between 15V and 20V to the word line of said selected memory page, and 5V to all other word lines in said selected memory sector, and all other word lines in said flash memory array are applied with 0V.

50. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein said write-row-decoder is further coupled to the select-gate lines of said flash memory array, but during a read operation of said flash memory array, said write-row-decoder is decoupled from all select-gate lines, and said read-row-decoder connects a boost voltage Vboost to one of select-gate lines in said flash memory array.

51. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, said write-row-decoder connects a power supply voltage Vdd or a boost voltage Vboost to all word lines in said selected memory sector, and all other word lines in said flash memory array are applied with 0V.

52. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, said read-row-decoder connects a boost voltage Vboost to the select-gate line of said selected memory page, and all other select-gate lines in said flash memory array are applied with 0V.

53. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein each of said NAND-based 2T-NOR flash cells has an access transistor which is a NAND-based double poly transistor having a poly1 floating gate shorted to a poly2 select gate.

54. The NAND-based 2T-NOR flash memory device as claimed in claim 53, wherein during a pre-program operation of said flash memory array, said read-row-decoder connects 0V to all select-gate lines in said flash memory array.

55. The NAND-based 2T-NOR flash memory device as claimed in claim 53, wherein during a page, block or sector erase operation in a selected memory sector, all select-gate lines in said selected memory sector are decoupled from said read-row-decoder so as to be floating and coupled to 20V, and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

56. The NAND-based 2T-NOR flash memory device as claimed in claim 53, wherein during a chip erase operation of said flash memory array, all select-gate lines in said flash memory array are decoupled from said read-row-decoder so as to be floating and coupled to 20V.

57. The NAND-based 2T-NOR flash memory device as claimed in claim 53, wherein during a page program operation of a selected memory page in a selected memory block of a selected memory sector, said read-row-decoder connects 5V to all select-gate lines in said selected memory sector, and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

58. The NAND-based 2T-NOR flash memory device as claimed in claim 53, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, said read-row-decoder connects a boost voltage Vboost to the select-gate line of said selected memory page, and all other select-gate lines in said flash memory array are applied with 0V.

59. The NAND-based 2T-NOR flash memory device as claimed in claim 35, wherein each of said NAND-based 2T-NOR flash cells has an access transistor made of a NAND-based single poly transistor having a poly1 or poly2 select gate.

60. The NAND-based 2T-NOR flash memory device as claimed in claim 59, wherein during a pre-program operation of said flash memory array, said read-row-decoder connects 0V to all select-gate lines in said flash memory array.

61. The NAND-based 2T-NOR flash memory device as claimed in claim 59, wherein during a page, block or sector erase operation in a selected memory sector, all select-gate lines in said selected memory sector are decoupled from said read-row-decoder so as to be floating and coupled to 20V, and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

62. The NAND-based 2T-NOR flash memory device as claimed in claim 59, wherein during a chip erase operation of said flash memory array, all select-gate lines in said flash memory array are decoupled from said read-row-decoder so as to be floating and coupled to 20V.

63. The NAND-based 2T-NOR flash memory device as claimed in claim 59, wherein during a page program operation of a selected memory page in a selected memory block of a selected memory sector, said read-row-decoder connects 5V to all select-gate lines in said selected memory sector, and all select-gate lines of all other memory sectors in said flash memory array are applied with 0V.

64. The NAND-based 2T-NOR flash memory device as claimed in claim 59, wherein during a read operation in a selected memory page of a selected memory block in a selected memory sector, said read-row-decoder connects a boost voltage Vboost to the select-gate line of said selected memory page, and all other select-gate lines in said flash memory array are applied with 0V.

65. A NAND-based two transistor NOR (2T-NOR) flash cell comprising:

a storage transistor having a cell gate connected to a word line running in an X direction, a first drain, and a first source connected to a source line running in a Y direction perpendicular to said word line; and

an access transistor having a select gate, a second source connected to said first drain of said storage transistor, and a second drain connected to a bit line running in parallel with said source line;

wherein said storage and access transistors are NAND-based double-poly transistors each having a floating gate, said cell gate and said select gate are poly2 gates, and the two floating gates are made of a poly1 layer underneath the two poly2 gates.

66. The 2T-NOR flash cell as claimed in claim 65, wherein said 2T-NOR flash cell is a single-level cell, said access transistor has a threshold voltage substantially centered at 0.75V in a range between 0.5V and 1V, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

67. The 2T-NOR flash cell as claimed in claim 65, wherein said 2T-NOR flash cell is a multi-level cell, said access transistor has a threshold voltage substantially centered at 0.75V in a range between 0.5V and 1V, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.

68. The 2T-NOR flash cell as claimed in claim 65, wherein erase and program operations of said 2T-NOR flash cell are based on a Fowler-Nordheim channel tunneling process with no voltage difference between said first drain and said first source of said storage transistor.

69. The 2T-NOR flash cell as claimed in claim 65, wherein the poly1 floating gate and said select gate of said access transistor are shorted together.

70. The 2T-NOR flash cell as claimed in claim 69, wherein said 2T-NOR flash cell is a single-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 layer, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

71. The 2T-NOR flash cell as claimed in claim 69, wherein said 2T-NOR flash cell is a multi-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 layer, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.

72. A NAND-based two transistor NOR (2T-NOR) flash cell comprising:

a storage transistor having a cell gate connected to a word line running in an X direction, a first drain and a first source connected to a source line running in a Y direction perpendicular to said word line; and

an access transistor having a select gate, a second source connected to said first drain of said storage transistor and a second drain connected to a bit line running in parallel with said source line;

wherein said storage transistor is a NAND-based double-poly transistor with said cell gate being a poly2 gate and a floating gate made of a poly1 layer underneath said poly2 gate, and said access transistor is a single-poly poly1 or poly2 NMOS transistor with said select gate being a poly1 or poly2 gate.

73. The 2T-NOR flash cell as claimed in claim 72, wherein said 2T-NOR flash cell is a single-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 or poly2 NMOS transistor, and said storage transistor has a first threshold voltage less than −

1V for an erased state and a second threshold voltage greater than 4V for a programmed state.

74. The 2T-NOR flash cell as claimed in claim 72, wherein said 2T-NOR flash cell is a multi-level cell, said access transistor has a threshold voltage which is a threshold voltage of said poly1 or poly2 NMOS transistor, and said storage transistor has a first threshold voltage less than −

1V for an erased state, a second threshold voltage in a range between 0V and 0.5V for a first programmed state and a third threshold voltage greater than 4V for a second programmed state.