×

Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design

  • US 20110157982A1
  • Filed: 07/02/2010
  • Published: 06/30/2011
  • Est. Priority Date: 07/10/2009
  • Status: Active Grant
First Claim
Patent Images

1. A NAND-based 2T-NOR flash memory array comprising:

  • a plurality of NAND-based 2T-NOR flash cells arranged in a two-dimensional array with a plurality of rows and a plurality of columns, each of said NAND-based 2T-NOR flash cells having a storage transistor with a cell gate, a source and a drain, and an access transistor with a select gate, a source and a drain, said source of said access transistor being connected in series with said drain of said storage transistor;

    a plurality of word lines with each word line connecting the cell gates of a row of said 2T-NOR flash cells, said word lines running in an X direction;

    a plurality of select-gate lines with each select-gate line connecting the select gates of a row of said 2T-NOR flash cells;

    a plurality of source lines with each source line connecting the sources of the storage transistors of one and only one column of said 2T-NOR flash cells, said source lines running in a Y direction perpendicular to said word lines;

    a plurality of bit lines with each bit line connecting the drains of the access transistors of one and only one column of said 2T-NOR flash cells, said bit lines running in parallel with said source lines; and

    wherein said NAND-based 2T-NOR flash memory array is partitioned into a plurality of memory sectors, each memory sector having a plurality of memory blocks, each memory block having a plurality of memory pages, and each memory page having one row of said NAND-based 2T-NOR flash cells with one word line and one select-gate line.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×