APPARATUS, SYSTEM, AND METHOD FOR BIASING DATA IN A SOLID-STATE STORAGE DEVICE

• US 20110157992A1
• Filed: 12/29/2010
• Published: 06/30/2011
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Wood, Robert, Peterson, James, Flynn, David, Thatcher, Jonathan, Fillingim, Jeremy, Strasser, John, Smith, Lance
• Granted Patent: US 8,189,407 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for improving performance in a non-volatile solid-state storage device. Non-volatile solid-state storage media includes a plurality of storage cells. The plurality of storage cells is configured such that storage cells in an empty state store initial binary values that satisfy a bias. An input module receives source data for storage in the plurality of storage cells of the non-volatile solid-state storage media. Bits of the source data have a source bias that is different from the bias of the plurality of storage cells. A bit biasing module biases the bits of the source data toward the bias of the plurality of storage cells. A write module writes the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.

Claims

1. A method to improve performance in a non-volatile solid-state storage device, the method comprising:

providing non-volatile solid-state storage media comprising a plurality of storage cells, the plurality of storage cells configured such that storage cells in an empty state store initial binary values that satisfy a bias;

receiving source data for storage in the plurality of storage cells of the non-volatile solid-state storage media, bits of the source data having a source bias different from the bias of the plurality of storage cells;

biasing the bits of the source data toward the bias of the plurality of storage cells; and

writing the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.

2. The method of claim 1, further comprising reading the biased source data from the plurality of storage cells of the non-volatile solid-state storage media and converting the bits of the biased source data back to original bit values for the source data such that a bias of the bits returns to the source bias.

3. The method of claim 1, further comprising determining that the source bias of the source data is different from the bias of the plurality of storage cells.

4. The method of claim 1, further comprising storing an indicator for the biased source data to indicate that the bits of the biased source data have been biased.

5. The method of claim 1, further comprising shifting the bits within the source data according to a reversible algorithm such that a start position for data and metadata within the source data changes between writing the biased source data to the plurality of storage cells and writing subsequent biased source data to the plurality of storage cells.

6. The method of claim 1, wherein the bias of the plurality of storage cells is selected from the group consisting of a bias toward ones, a bias toward zeroes, and a bias toward a balance of ones and zeroes.

7. The method of claim 1, wherein the bias of the plurality of storage cells comprises a bias toward a binary pattern.

8. The method of claim 7, wherein the binary pattern is selected based on a state of one or more other storage cells physically adjacent to the plurality of storage cells.

9. The method of claim 8, wherein the binary pattern satisfies a predefined voltage differential threshold between the one or more other storage cells and the plurality of storage cells.

10. The method of claim 1, wherein biasing the bits of the source data comprises flipping binary values of the bits to satisfy the bias of the plurality of storage cells.

11. The method of claim 1, wherein biasing the bits comprises pseudo-randomizing the values of the bits of the source data.

12. The method of claim 1, wherein biasing the bits comprises,

retrieving a preset sequence number associated with the plurality of storage cells;

entering the preset sequence number into a pseudo-random number generator as a seed value to obtain a pseudo-random binary sequence; and

biasing the bits of the source data toward the bias of the plurality of storage cells by pseudo-randomizing the values of the bits of the source data using the pseudo-random binary sequence.

13. The method of claim 12, wherein the preset sequence number comprises a sequence number of an erase block associated with the plurality of storage cells, the preset sequence number stored in a predefined location in the erase block during an erase procedure such that the preset sequence number for the erase block changes with each erase procedure.

14. The method of claim 1, wherein biasing the bits comprises padding the source data with padding data having binary values that bias the source data toward the bias of the plurality of storage cells.

15. The method of claim 14, wherein biasing the bits further comprises compressing the source data and selecting a size of the padding data based on an amount of space gained by the compression.

16. The method of claim 1, wherein biasing the bits of the source data comprises biasing a plurality of bits of the source data such that storage cells of the source data storing the plurality of bits change state from original-state storage cells to active storage cells.

17. The method of claim 1, wherein biasing the bits of the source data comprises dividing the source data into a plurality of subsets of the source data and biasing the subsets of the source data, the subsets of the source data sized to fit a write data pipeline.

18. The method of claim 1, wherein biasing the bits of the source data comprises excluding the source data from application of a bias in response to the source data prior to biasing having a bias that matches the bias of the plurality of storage cells.

19. An apparatus to improve performance in a non-volatile solid-state storage device, the apparatus comprising:

non-volatile solid-state storage media comprising a plurality of storage cells, the plurality of storage cells configured such that storage cells in an empty state store initial binary values that satisfy a bias;

an input module that receives source data for storage in the plurality of storage cells of the non-volatile solid-state storage media, bits of the source data having a source bias different from the bias of the plurality of storage cells;

a bit biasing module that biases the bits of the source data toward the bias of the plurality of storage cells; and

a write module that writes the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.

20. The apparatus of claim 19, wherein the bit biasing module biases the bits by,

retrieving a preset sequence number associated with the plurality of storage cells;

entering the preset sequence number into a pseudo-random number generator as a seed value to obtain a pseudo-random binary sequence; and

biasing the bits of the source data toward the bias of the plurality of storage cells by pseudo-randomizing the values of the bits of the source data using the pseudo-random binary sequence.

21. A system to improve performance in a non-volatile solid-state storage device, the system comprising:

a processor;

one or more communications buses in communication with the processor;

non-volatile solid-state storage media comprising a plurality of storage cells, the plurality of storage cells configured such that storage cells in an empty state store initial binary values that satisfy a bias;

an input module that receives source data from the processor over the one or more communications buses for storage in the plurality of storage cells of the non-volatile solid-state storage media, bits of the source data having a source bias different from the bias of the plurality of storage cells;

a bit biasing module that biases the bits of the source data toward the bias of the plurality of storage cells; and

a write module that writes the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.

22. A method to improve performance in a non-volatile solid-state storage device, the method comprising:

providing non-volatile solid-state storage media comprising a plurality of storage cells;

receiving source data for storage in the plurality of storage cells of the non-volatile solid-state storage media;

shifting bits within the source data according to a reversible algorithm such that a start position for data and metadata within the source data changes between writing the source data to the plurality of storage cells and writing subsequent source data to the plurality of storage cells; and

writing the shifted source data to the plurality of storage cells of the non-volatile solid-state storage media.

23. The method of claim 22, further comprising biasing the bits of the source data toward a bias of the plurality of storage cells, wherein the plurality of storage cells are configured such that storage cells in an empty state store initial binary values that satisfy the bias of the plurality of storage cells and the bits of the source data as received have a source bias different from the bias of the plurality of storage cells.