TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME
First Claim
Patent Images
1. A tuner circuit comprising:
- a digital signal processor to generate a digital data stream related to a radio frequency signal; and
a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame comprising a start portion and a plurality of channels, the plurality of channels including a first data channel to carry a portion of the digital data stream and including a control channel to carry control data, the transceiver circuit configurable to send the inter-chip communication frame to an additional tuner circuit through the inter-chip communication link.
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Abstract
A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.
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Citations
22 Claims
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1. A tuner circuit comprising:
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a digital signal processor to generate a digital data stream related to a radio frequency signal; and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame comprising a start portion and a plurality of channels, the plurality of channels including a first data channel to carry a portion of the digital data stream and including a control channel to carry control data, the transceiver circuit configurable to send the inter-chip communication frame to an additional tuner circuit through the inter-chip communication link. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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generating a digital data stream and an associated signal quality metric related to a radio frequency signal at a digital signal processor of a tuner circuit; inserting a start symbol pattern into a start field of an inter-chip link frame using an inter-chip transmitter circuit; inserting a portion of the digital data stream into a first data field of the inter-chip link frame using the inter-chip transmitter circuit; inserting at least a portion of the associated signal quality metric into a second data field of the inter-chip link frame using the inter-chip transmitter circuit; and transmitting the inter-chip link frame to an additional tuner circuit through an inter-chip communication link. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An inter-chip transmitter circuit comprising:
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a first multiplexer having a first input to receive a portion of a digital data stream related to a radio frequency signal, a second input to receive an associated signal metric, and a third input to receive control data; a second multiplexer having a first input to receive a start pattern and a second input coupled to an output of the first multiplexer; a control circuit configurable to control the first and second multiplexers to produce an inter-chip link frame including a start field to carry a symbol related to the start pattern, a first data field to carry a symbol related to the portion of the digital data stream, a second data field to carry signal data, and a control field to carry the control data; and a driver circuit configurable to send the inter-chip link frame to an additional tuner circuit through an inter-chip communication link. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification