SYSTEM AND METHOD FOR BI-PHASE MODULATION DECODING

• US 20110158329A1
• Filed: 03/10/2011
• Published: 06/30/2011
• Est. Priority Date: 12/23/2009
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Heminger, Mark David, Oettinger, Eric Gregory, Hagen, Mark David
• Application Number:
  US13/044,930
• Publication Number:
  US 20110158329A1
• Time in Patent Office: Days
• US Class Current: 375/258
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: H04L 2027/003 at baseband only
• CPC Class Codes: H04L 2027/0046 Open loops
• CPC Class Codes: H04L 2027/0069 Loop filters
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/2338 using sampling H04L27/2331 - H04L27/2335 take precedence

Abstract

One embodiment of the present invention includes a decoder system that decodes a bi-phase modulated signal. The system includes a buffer configured to store a first plurality of digital samples associated with a first bit of the bi-phase modulated signal and a second plurality of digital samples associated with a second bit of the bi-phase modulated signal. The first bit can immediately precede the second bit. The system also includes a first summer configured to add the first plurality of digital samples to generate a first sum and a second summer configured to add the second plurality of digital samples to generate a second sum. The system further includes a comparator configured to compare the first sum and the second sum to determine an edge-transition between the first bit and the second bit, and to determine a logic-state of the first bit based on the edge-transition.

Claims

1. A decoder system that decodes a bi-phase modulated signal, the system comprising:

a buffer configured to store a first plurality of digital samples associated with a first bit of the bi-phase modulated signal and a second plurality of digital samples associated with a second bit of the bi-phase modulated signal, the first bit immediately preceding the second bit;

a first summer configured to add the first plurality of digital samples to generate a first sum;

a second summer configured to add the second plurality of digital samples to generate a second sum; and

a comparator configured to compare the first sum and the second sum to determine an edge-transition between the first bit and the second bit, and to determine a logic-state of the first bit based on the edge-transition.

2. The system of claim 1, wherein the first plurality of digital samples comprise a plurality of samples associated with a second half of a total number of samples associated with the first bit and wherein the second plurality of digital samples comprise a plurality of samples associated with a first half of a total number of samples associated with the second bit.

3. The system of claim 2, wherein the total number of samples associated with each of the first and second bits comprises X bits, where X is a positive integer, and wherein the plurality of samples associated with each of the second half and the first half of the total number of samples associated with each of the first and second bits, respectively, comprises Y bits, where Y is a positive integer that is less than X/2 bits, rounded down.

4. The system of claim 1, wherein the buffer is configured to store a total plurality of digital samples that comprises the first and second pluralities of digital samples, the system further comprising a controller configured to identify a quantity of the total plurality of digital samples that correspond to a given bit of the bi-phase modulated signal.

5. The system of claim 4, wherein the integrator is configured to identify the quantity of the total plurality of digital samples that correspond to the given bit of the bi-phase modulated signal based on an average of digital samples comprising the first and second pluralities of digital samples relative to one of a median digital sample and an average of a pair of digital samples that correspond to an expected location of the edge-transition between the first and second bits associated with the first and second pluralities of digital samples.

6. The system of claim 5, wherein the integrator is configured to determine a location of the edge-transition between two consecutive digital samples of the total plurality of digital samples based on the average.

7. The system of claim 6, wherein the integrator is further configured to determine which of the total plurality of digital samples stored in the buffer correspond to the first plurality of digital samples and the second plurality of digital samples, respectively, based on the location of the edge-transition.

8. The system of claim 1, wherein an output of the comparator is determinative of the logic-state of the second bit based on the edge-transition by comparing the edge-transition with a previous edge-transition between the first bit and an immediately preceding bit.

9. The system of claim 8, wherein the comparator is configured to determine that the second bit has a logic-high state based on the edge-transition being substantially equal to the previous edge-transition and to determine that the second bit has a logic-low state based on the edge-transition being opposite of the previous edge-transition.

10. A wireless power system comprising the decoder system of claim 1, the wireless power system comprising:

a wireless charger comprising a receiver configured to monitor a primary current associated with a primary inductor, the receiver comprising the decoder system of claim 1; and

a portable electronic device comprising a transmitter configured to modulate the bi-phase communication signal onto a secondary current associated with a secondary inductor, the primary inductor and secondary inductor collectively forming an isolation transformer configured to transfer energy from the primary inductor to the secondary inductor to generate a voltage in the portable electronic device.

11. The wireless power system of claim 10, the receiver further comprising an analog-to-digital converter (ADC) configured to convert a magnitude of one of a voltage, a power, and a current associated with the primary inductor into the plurality of digital samples of the bi-phase modulated signal.

12. A method for decoding a bi-phase modulated signal, the method comprising:

receiving the bi-phase modulated signal via a transmission medium;

converting the bi-phase modulated signal from an analog form to a digital form comprising a plurality of digital samples;

storing the plurality of digital samples in a buffer;

adding a first portion of the plurality of digital samples to generate a first sum associated with a first bit of the bi-phase modulated signal;

adding a second portion of the plurality of digital samples to generate a second sum associated with a second bit of the bi-phase modulated signal, the second bit immediately following the first bit in the bi-phase modulated signal;

comparing the first sum and the second sum to determine an edge-transition between the first bit and the second bit; and

determining a logic-state of the first bit based on the edge-transition relative to an immediately preceding edge-transition between the first bit and an immediately preceding bit.

13. The method of claim 12, wherein adding the first portion of the plurality of digital samples comprises adding the first portion of the plurality of digital samples associated with a second half of a total number of samples associated with the first bit to generate the first sum, and wherein adding the second portion of the plurality of digital samples comprises adding the second portion of the plurality of digital samples associated with a first half of a total number of samples associated with the second bit to generate the second sum.

14. The method of claim 13, further comprising discarding at least one sample from the first and second portions of the plurality of digital samples symmetrically about the edge-transition prior to adding the first portion to generate the first sum and adding the second portion to generate the second sum.

15. The method of claim 12, further comprising generating an average of an expected number of samples corresponding to the first and second pluralities of digital samples to determine a quantity of the plurality of digital samples that correspond to a given bit of the bi-phase modulated signal.

16. The method of claim 15, further comprising:

determining a location of the edge-transition between two consecutive digital samples of the plurality of digital samples based on the average; and

determining which of the plurality of digital samples stored in the buffer correspond to the first plurality of digital samples and the second plurality of digital samples, respectively, based on the location of the edge-transition.

17. A wireless power system comprising:

a portable electronic device comprising a transmitter configured to modulate a bi-phase communication signal onto a secondary current associated with a secondary inductor; and

a wireless charger comprising a receiver configured to monitor a primary current associated with a primary inductor, the primary inductor and secondary inductor collectively forming an isolation transformer configured to transfer energy from the primary inductor to the secondary inductor to generate a voltage in the portable electronic device, the receiver comprising a decoder comprising;

a buffer configured to store a first plurality of digital samples associated with a second half of a total number of samples of a first bit of the bi-phase modulated signal and a second plurality of digital samples associated with a second half of a total number of samples of a second bit of the bi-phase modulated signal, the first bit immediately preceding the second bit;

a first summer configured to add the first plurality of digital samples to generate a first sum;

a second summer configured to add the second plurality of digital samples to generate a second sum; and

a comparator configured to compare the first sum and the second sum to determine an edge-transition between the first bit and the second bit, and to determine a logic-state of the second bit based on comparing the edge-transition with a previous edge-transition between the first bit and an immediately preceding bit.

18. The wireless power system of claim 17, the receiver further comprising an analog-to-digital converter (ADC) configured to convert a magnitude of the primary current into the plurality of consecutive digital samples of the bi-phase modulated signal.

19. The wireless power system of claim 17, wherein the total number of samples associated with each of the first and second bits comprises X bits, where X is a positive integer, and wherein the plurality of samples associated with each of the second half and the first half of the total number of samples associated with each of the first and second bits, respectively, comprises Y bits, where Y is a positive integer that is less than X/2 bits, rounded down.

20. The wireless power system of claim 17, wherein the buffer is configured to store a total plurality of digital samples that comprises the first and second pluralities of digital samples, the system further comprising an integrator configured to identify a location of the edge-transition between two consecutive digital samples based on an average of digital samples comprising the first and second pluralities of digital samples, and to determine which of the total plurality of digital samples stored in the buffer correspond to the first plurality of digital samples and the second plurality of digital samples, respectively, based on the location of the edge-transition.