Thin film transistors and methods of manufacturing the same

• US 20110159646A1
• Filed: 03/04/2011
• Published: 06/30/2011
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Jang-Yeon Kwon, Ji-Sim Jung, Kyung-Bae Park, Kyung-Seok Son, Myung-Kwan Ryu, Tae-Sang Kim
• Original Assignee: Jang-Yeon Kwon, Ji-Sim Jung, Kyung-Bae Park, Kyung-Seok Son, Myung-Kwan Ryu, Tae-Sang Kim
• Inventors: Son, Kyung-seok, Ryu, Myung-kwan, Jung, Ji-sim, Kim, Tae-sang, Park, Kyung-bae, Kwon, Jang-yeon
• Granted Patent: US 8,349,647 B2
• Time in Patent Office: Days
• US Class Current: 438/156
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT includes a zinc oxide (ZnO)-based channel layer having a plurality of semiconductor layers. An uppermost of the plurality of semiconductor layers has a Zn concentration less than that of a lower semiconductor layer to suppress an oxygen vacancy due to plasma. The uppermost semiconductor layer of the channel layer also has a tin (Sn) oxide, a chloride, a fluoride, or the like, which has a relatively stable bonding energy against plasma. The uppermost semiconductor layer is relatively strong against plasma shock and less decomposed when being exposed to plasma, thereby suppressing an increase in carrier concentration.

Claims

1. A method of manufacturing a thin-film-transistor (TFT), the method comprising:

forming a zinc oxide (ZnO)-based channel layer on a substrate, the ZnO-based channel layer including a plurality of ZnO-based semiconductor layers, a Zn concentration of an uppermost semiconductor layer of the plurality of ZnO-based semiconductor layers less than a Zn concentration of at least one other of the plurality of semiconductor layers;

forming a source electrode and a drain electrode at respective sides of the channel layer; and

forming a passive layer covering the channel layer, the source electrode, and the drain electrode.

2. The method of claim 1, wherein the uppermost semiconductor layer includes a Sn oxide.

3. The method of claim 1, wherein the uppermost semiconductor layer includes at least one of a chloride and a fluoride.

4. The method of claim 3, wherein the uppermost semiconductor layer includes Sn oxide.

5. The method of claim 1, wherein the ZnO-based channel layer is gallium-indium-zinc-oxide (GIZO).

6. The method of claim 1, wherein the forming of the source electrode and the drain electrode includes,

forming a metal layer,

forming a mask having a pattern corresponding to the channel layer on the metal layer, and

patterning the metal layer using the mask to form a source electrode and a drain electrode.

7. The method of claim 6, wherein the patterning of the metal layer includes,

etching the metal layer using an etch gas containing at least one of a chlorine (Cl)-based gas and a fluorine (F)-based gas.

8. The method of claim 1, further comprising:

forming a gate on the substrate; and

forming a gate insulating layer covering the gate on the substrate,

wherein the forming of the ZnO-based channel layer includes forming a ZnO-based channel material layer on the gate insulating layer, the ZnO-based channel material layer including a ZnO-based lower semiconductor layer and a ZnO-based upper semiconductor layer, a Zn concentration of the ZnO-based upper semiconductor layer less than a Zn concentration of the ZnO-based lower semiconductor layer,

forming a mask layer on the channel material layer, the mask layer having a pattern corresponding to a channel, source and drain regions, the source and drain regions contacting respective sides of the channel region, and

patterning the channel material layer using the mask layer to form a channel layer.

9. The method of claim 8, wherein the forming of the source and drain electrodes includes,

patterning the channel material layer by dry etching using an etch gas including a least one of a Cl-based gas and a F-based gas, and

inducing bonding between at least one material in the channel material layer and at least one of Cl and F in the etch gas on a portion of the channel layer exposed to the plasma gas during the patterning, the induced bonding forming at least one of a chloride and a fluoride in the channel layer.

10. The method of claim 8, further comprising:

removing the source and drain regions from the mask layer to expose sides of the channel layer;

performing plasma treatment on the exposed sides of the channel layer to form ohmic contact layers;

removing the mask layer; and

forming source and drain electrodes covering the ohmic contact layers on both sides of the channel layer.

11. The method of claim 10, wherein a portion of the mask layer corresponding to the channel region is thicker than portions of the mask layer corresponding to the source and drain regions, and

the source and drain regions are removed from the mask layer by ashing the mask layer.

12. The method of claim 1, further comprising:

forming a gate on the substrate; and

forming a gate insulating layer covering the gate,

wherein a first portion of the channel layer is formed directly on the gate and a second portion of the channel layer is formed directly on the substrate.