METHOD TO FORM A SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC LAYERS OF VARYING THICKNESSES

• US 20110159678A1
• Filed: 12/30/2009
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Da-Yuan, Lee, Wei-Yang, Tao, Hun-Jan, Hsu, Kuang-Yuan
• Granted Patent: US 8,008,143 B2
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for fabricating an integrated circuit device is disclosed. An exemplary method can include providing a substrate having a first region, a second region, and a third region; and forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.

Claims

1. A method for fabricating an integrated circuit device having gate dielectric layers of varying thicknesses, the method comprising:

providing a substrate with a first region, a second region, and a third region;

forming a first gate structure in the first region, wherein the first gate structure includes a first gate dielectric layer having a first thickness, a barrier layer, and a dummy gate layer;

forming a second gate structure in the second region, wherein the second gate structure includes a dummy gate dielectric layer and the dummy gate layer;

forming a third gate structure in the third region, wherein the third gate structure includes the dummy gate dielectric layer and the dummy gate layer;

removing the dummy gate layer from the first, second, and third gate structure, thereby forming openings in the first, second, and third gate structures;

performing an implantation process in the second region;

removing the dummy gate dielectric layer from the openings of the second and third gate structures;

forming an interfacial dielectric layer to partially fill in the openings of the second and third gate structures, wherein the interfacial dielectric layer of the second gate structure has a second thickness and the interfacial dielectric layer of the third gate structure has a third thickness; and

forming a gate in the openings of the first, second, and third gate structures.

2. The method of claim 1 wherein performing the implantation process in the second region comprises modifying an oxidation rate of the second region.

3. The method of claim 1 wherein performing the implantation process in the second region comprises utilizes a doping species selected from the group consisting of indium (In), argon (Ar), silicon (Si), fluorine (F), and combinations thereof.

4. The method of claim 1 wherein forming the first gate structure including the barrier layer comprises forming a silicon nitride layer over the first gate dielectric layer having the first thickness.

5. The method of claim 4 wherein forming the silicon nitride layer comprises performing a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a plasma enhanced CVD process, or a plasma enhanced ALD process.

6. The method of claim 1 wherein forming the first gate structure including the barrier layer comprises forming a nitridation layer over the first gate dielectric layer having the first thickness.

7. The method of claim 6 wherein forming the nitridation layer comprises performing a thermal nitridation using an ammonia gas (NH₃).

8. The method of claim 6 wherein forming the nitridation layer comprises performing a plasma nitridation process.

9. The method of claim 6 wherein forming the nitridation layer comprises performing an in-situ doping process.

10. The method of claim 1 wherein forming the gate in the openings of the first, second, and third gate structures comprises forming a high-k dielectric layer and conductive layer to fill the openings of the first, second, and third gate structures.

11. A method for fabricating an integrated circuit device, the method comprising:

providing a substrate having a first region, a second region, and a third region;

forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure; and

wherein forming the gate dielectric layer of the first, second, and third thicknesses includes;

while forming the first, second, and third gate structures, forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions; and

prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one of the first, second, or third regions.

12. The method of claim 11 wherein forming the etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions comprises depositing a silicon nitride (SiN) layer.

13. The method of claim 11 wherein forming the etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions comprises forming a nitridation layer.

14. The method of claim 11 wherein performing the implantation process on at least one of the first, second, or third regions comprises implanting the at least one region with a doping species selected from the group consisting of indium (In), argon (Ar), silicon (Si), fluorine (F), and combinations thereof.

15. A method for fabricating an integrated circuit device having gate dielectric layers of varying thicknesses, the method comprising:

providing a substrate with a first region, a second region, and a third region;

forming a first gate dielectric layer having a first thickness in the first region;

forming a barrier layer over the first gate dielectric layer;

forming a dummy gate dielectric layer in the second and third regions;

forming a dummy gate layer over the barrier layer and the dummy gate dielectric layer;

performing a gate patterning process to form gate structures in the first, second, and third regions;

removing the dummy gate layer from the gate structures in the first, second, and third regions, thereby forming openings in the gate structures in the first, second, and third regions;

performing an implantation process in the second or third region;

removing the dummy gate dielectric layer from the openings of the gate structures in the second and third regions;

forming an interfacial layer to partially fill in the openings of the gate structures in the second and third regions, wherein the interfacial layer in the second region exhibits a second thickness and the interfacial layer in the third region exhibits a third thickness.

16. The method of claim 15 wherein performing the implantation process in the second or third region comprises modifying an oxidation rate in the second or third region.

17. The method of claim 16 wherein modifying the oxidation rate in the second or third region comprises increasing the oxidation rate in the second region, wherein forming the interfacial layer results in the second thickness being greater than the third thickness.

18. The method of claim 15 wherein forming the barrier layer over the first gate dielectric layer comprises forming a barrier layer including a nitride material.

19. The method of claim 15 wherein forming the interfacial layer to partially fill in the openings of the gate structures in the second and third regions further comprises:

removing the barrier layer from the opening of the gate structure in the first region; and

forming the interfacial layer to partially fill in the opening of the gate structure in the first region.

20. The method of claim 15 wherein forming the gate structures in the first, second, and third regions comprises forming spacers for each gate structure.