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DATA STORAGE AND ACCESS IN MULTI-CORE PROCESSOR ARCHITECTURES

  • US 20110161346A1
  • Filed: 12/30/2009
  • Published: 06/30/2011
  • Est. Priority Date: 12/30/2009
  • Status: Active Grant
First Claim
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1. A system for sending a data block stored in a cache, the system comprising:

  • a first processor in a first tile, the first processor effective to generate a request for a data block, the request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the first tile; and

    a second tile effective to receive the request from the first tile, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request received from the first tile to the data tile;

    whereinthe data tile is effective to receive the request from the second tile, the data tile further effective to send the data block to the destination tile identified by the destination identifier.

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