DATA STORAGE AND ACCESS IN MULTI-CORE PROCESSOR ARCHITECTURES
First Claim
1. A system for sending a data block stored in a cache, the system comprising:
- a first processor in a first tile, the first processor effective to generate a request for a data block, the request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the first tile; and
a second tile effective to receive the request from the first tile, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request received from the first tile to the data tile;
whereinthe data tile is effective to receive the request from the second tile, the data tile further effective to send the data block to the destination tile identified by the destination identifier.
4 Assignments
0 Petitions
Accused Products
Abstract
Technologies are generally described for a system for sending a data block stored in a cache. In some examples described herein, a system may comprise a first processor in a first tile. The first processor is effective to generate a request for a data block, the request including a destination identifier identifying a destination tile for the data block, the destination tile being distinct from the first tile. Some example systems may further comprise a second tile effective to receive the request, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request to the data tile. Some example systems may still further comprise a data tile effective to receive the request from the second tile, the data tile effective to send the data block to the destination tile.
34 Citations
25 Claims
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1. A system for sending a data block stored in a cache, the system comprising:
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a first processor in a first tile, the first processor effective to generate a request for a data block, the request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the first tile; and a second tile effective to receive the request from the first tile, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request received from the first tile to the data tile;
whereinthe data tile is effective to receive the request from the second tile, the data tile further effective to send the data block to the destination tile identified by the destination identifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for sending a data block stored in a cache, the method comprising:
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generating a request for a data block by a first processor in a first tile, the request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the first tile; receiving the request by a second tile from the first tile; determining, by a second processor in the second tile, a data tile including the data block; sending, by the second processor, the request received from the first tile to the data tile; receiving the request by the data tile from the second tile; and sending, by a third processor in the data tile, the data block to the destination tile identified by the destination identifier. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A computer storage medium having computer-executable instructions stored thereon which, when executed by a computer, adapt the computer to perform the method comprising:
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generating a request for a data block by a first processor in a first tile, the request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the first tile; receiving the request by a second tile from the first tile; determining, by a second processor in the second tile, a data tile including the data block; sending, by the second processor, the request received from the first tile to the data tile; receiving the request by the data tile from the second tile; and sending, by a third processor in the data tile, the data block to the destination tile identified by the destination identifier. - View Dependent Claims (22, 23)
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24. A tile in a multi-processor architecture, the tile comprising:
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a processor, the processor effective to generate a first request for a data block, the first request including a destination identifier that includes an identification of a destination tile for the data block, the destination tile being distinct from the tile including the processor; the processor effective to send the first request from the tile including the processor to a second tile; a table, the table effective to indicate that the data block is stored in the destination tile; the processor further effective to generate a second request to access the data block; the first processor effective to search the table to determine if the destination tile is indexed in the table; and when the destination tile is determined to be indexed in the table, the processor is effective to send the second request from the tile including the processor to the destination tile; when the destination tile is determined to be absent from the table, the processor is effective to send the second request from the tile including the processor to the second tile. - View Dependent Claims (25)
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Specification