HARDWARE SUPPORTED HIGH PERFORMANCE LOCK SCHEMA
First Claim
1. A method for performing lock allocation for a plurality of processor cores, and wherein a first processor core acquires a lock, while other processor cores that need to acquire said lock are in sleep state, the method including:
- receiving a signal that the first processor core has released said lock;
determining a second processor core that should be woken up from other processor cores that need to acquire said lock and are in sleep state based on a predetermined rule for allocating said lock; and
waking up the second processor core to enable it to acquire said lock.
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Accused Products
Abstract
A method and apparatus for lock allocation control. When a processor core acquires a lock, other processor cores do not need to constantly poll memory to check whether the required lock is released. Instead, other processor cores will be in sleep state and the next processor core needed will be selectively woken up based on predetermined rule, such that an out-of-order lock contention procedure is turned into an in-order lock allocation procedure. By selectively waking up a processor core that is in sleep state, the method and apparatus can avoid occupying a large amount of bus bandwidth, can avoid cache misses, and can save power consumption of chip.
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Citations
19 Claims
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1. A method for performing lock allocation for a plurality of processor cores, and wherein a first processor core acquires a lock, while other processor cores that need to acquire said lock are in sleep state, the method including:
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receiving a signal that the first processor core has released said lock; determining a second processor core that should be woken up from other processor cores that need to acquire said lock and are in sleep state based on a predetermined rule for allocating said lock; and waking up the second processor core to enable it to acquire said lock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A lock allocation controller for performing lock allocation for a plurality of processor cores, and wherein a first processor core acquires a lock, while other processor cores that need to acquire said lock are in sleep state, the lock allocation controller including:
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a lock state change receiving means for receiving a signal that the first processor core has released said lock; a target core determining means for determining a second processor core that is in sleep state and should be woken up from other processor cores that need to acquire said lock and are in sleep state based on predetermined rule for allocating said lock; and a target core waking up means for waking up the second processor core to enable it to acquire said lock. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A computer system comprising:
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a plurality of processor cores; at least one cache; and lock allocation controller for performing lock allocation for a plurality of processor cores, and wherein a first processor core acquires a lock, while other processor cores that need to acquire said lock are in sleep state, the lock allocation controller including; a lock state change receiving means for receiving a signal that the first processor core has released said lock; a target core determining means for determining a second processor core that is in sleep state and should be woken up from other processor cores that need to acquire said lock and are in sleep state based on predetermined rule for allocating said lock; and a target core waking up means for waking up the second processor core to enable it to acquire said lock.
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Specification