SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS

• US 20110161589A1
• Filed: 12/30/2009
• Published: 06/30/2011
• Est. Priority Date: 12/30/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Puzak, Thomas R., Starke, William J., Stuecheli, Jeffrey A., Williams, Derek E., Guthrie, Guy L.
• Granted Patent: US 9,189,403 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/12 Replacement control

Abstract

A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including first and second processing units and a system memory coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:

in response to a data request;

selecting a victim cache line to be castout from the first lower level cache;

the first lower level cache deciding, based upon a confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory;

in response to the first lower level cache deciding to perform the LCO;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric and removing the victim cache line from the first lower level cache; and

the second lower level cache holding the victim cache line.

3. The method of claim 1, wherein:

the first lower level cache includes a cache directory;

the cache directory includes a chronology vector indicating an access order in a congruence class containing the victim cache line; and

the method further comprises setting the confidence indicator associated with the victim cache line in response to an access by the first processor core to the victim cache line while the victim cache line has at least a predetermined position in the access order.

4. The method of claim 1, wherein the selecting includes:

determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class; and

selecting as the victim cache line one of one or more cache lines in the second class.

5. The method of claim 4, and further comprising maintaining in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

6. The method of claim 1, wherein said lateral castout command identifies the second lower level cache as the destination.

7. The method of claim 1, and further comprising:

in response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit transmitting the victim cache line to the second lower level cache.

8. The method of claim 1, wherein said deciding further comprises the first lower level cache deciding, based upon a coherence state associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory.

9. A data processing system, comprising:

an interconnect fabric;

a system memory coupled to the interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;

wherein the first lower level cache, responsive to a data request, selects a victim cache line to be castout from the first lower level cache and decides, based upon a confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory;

wherein the first processing unit, responsive to the first lower level cache deciding to perform the LCO, issues a lateral castout (LCO) command on the interconnect fabric and removes the victim cache line from the first lower level cache; and

wherein the second lower level cache, responsive to the LCO command, holds the victim cache line.

10. The data processing system of claim 9, wherein the first and second lower level caches are victim caches.

11. The data processing system of claim 9, wherein:

the first lower level cache includes a cache directory;

the cache directory includes a chronology vector indicating an access order in a congruence class containing the victim cache line; and

the first lower level cache sets the confidence indicator associated with the victim cache line in response to an access by the first processor core to the victim cache line while the victim cache line has at least a predetermined position in the access order.

12. The data processing system of claim 9, wherein the first lower level cache selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines in the second class.

13. The data processing system of claim 12, wherein the first lower level cache maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

14. The data processing system of claim 9, wherein said lateral castout command identifies the second lower level cache as the destination.

15. The data processing system of claim 9, wherein the first processing unit, responsive to a coherence response to the LCO command indicating success of the LCO command, transmits the victim cache line to the second lower level cache.

2. The method of claim 1, wherein the first and second lower level caches are victim caches.

16. The data processing system of claim 9, wherein the first lower level cache further decides between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory based upon a coherence state associated with the victim cache line.

17. The processing unit of claim 15, wherein:

the first lower level cache includes a cache directory;

the cache directory includes a chronology vector indicating an access order in a congruence class containing the victim cache line; and

the first lower level cache sets the confidence indicator associated with the victim cache line in response to an access by the first processor core to the victim cache line while the victim cache line has at least a predetermined position in the access order.

18. The processing unit of claim 15, wherein the first lower level cache selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and selecting as the victim cache line one of one or more cache lines in the second class.

19. The processing unit of claim 18, wherein the first lower level cache maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

20. The processing unit of claim 15, wherein said lateral castout command identifies the second lower level cache as the destination.

21. The processing unit of claim 15, wherein the first processing unit, responsive to a coherence response to the LCO command indicating success of the LCO command, transmits the victim cache line to the second lower level cache.

22. The processing unit of claim 15, wherein the first lower level cache further decides between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory based upon a coherence state associated with the victim cache line.

15-1. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, wherein the processing unit is first processing unit among the plurality of processing units and the plurality of processing units further includes a second processing unit including a second processor core and associated second upper and lower level caches, the first processing unit comprising:

a first processor core and associated first upper and first lower level caches;

wherein the first lower level cache, responsive to a data request, selects a victim cache line to be castout from the first lower level cache and decides, based upon a confidence indicator associated with the victim cache line, between performing a lateral castout (LCO) of the victim cache line to another lower level cache and a castout of the victim cache line to the system memory;

wherein the first processing unit, responsive to the first lower level cache deciding to perform the LCO, issues a lateral castout (LCO) command on the interconnect fabric and removes the victim cache line from the first lower level cache; and

wherein the second lower level cache, responsive to the LCO command, holds the victim cache line.

16-2. The processing unit of claim 15, wherein the first and second lower level caches are victim caches.