SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS
First Claim
1. A process for forming an integrated circuit interconnect structure, said process comprising:
- a) providing a partially-completed and planarized interconnect structure comprising an electrically insulating surface and an electrically conductive, copper-containing surface;
b) depositing a protecting agent that comprises two or more compounds over said electrically insulating surface to synergistically reduce affinity of said electrically insulating surface to a precursor comprising manganese, cobalt, chromium or vanadium;
c) selectively depositing a metal selected from the group consisting of manganese, cobalt, chromium and vanadium on at least a part of the electrically conductive copper-containing surface.
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Accused Products
Abstract
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.
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Citations
45 Claims
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1. A process for forming an integrated circuit interconnect structure, said process comprising:
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a) providing a partially-completed and planarized interconnect structure comprising an electrically insulating surface and an electrically conductive, copper-containing surface; b) depositing a protecting agent that comprises two or more compounds over said electrically insulating surface to synergistically reduce affinity of said electrically insulating surface to a precursor comprising manganese, cobalt, chromium or vanadium; c) selectively depositing a metal selected from the group consisting of manganese, cobalt, chromium and vanadium on at least a part of the electrically conductive copper-containing surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A process for forming an integrated circuit interconnect structure, said process comprising:
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a) providing a partially-completed interconnect structure having one or more vias and trenches, said vias and trenches comprising sidewalls defined by one or more electrically insulating materials and electrically conductive copper-containing bottom regions; b) depositing a layer comprising a nitride of a metal selected from the group consisting of manganese, chromium and vanadium on the partially-completed interconnect structure; c) depositing copper within said one or more vias and trenches. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A process comprising:
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depositing a metal containing layer from a vapor of a metal containing precursor, wherein the metal is selected from the group consisting of manganese, chromium and vanadium; depositing an iodine or bromine containing material from a vapor of an iodine or bromine containing precursor, wherein the iodine or bromine containing material is chemisorbed on or in the metal containing layer; and depositing a copper containing material from a vapor of a copper containing precursor, wherein the iodine or bromine containing material allows a catalytic deposition of copper containing material. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification