High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates

• US 20110163375A1
• Filed: 02/14/2011
• Published: 07/07/2011
• Est. Priority Date: 12/04/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Fei-Yuh, Liao, Chun-Ting, Chu, Chen-Liang, Huang, Tsung-Yi
• Granted Patent: US 8,183,626 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a high-voltage well (HVW) region in the semiconductor substrate;

a first double diffusion (DD) region in the HVW region;

a second DD region in the HVW region, wherein the first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region;

a recess extending from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region;

a gate dielectric extending into the recess and covering a bottom of the recess;

a gate electrode over the gate dielectric;

a first source/drain region in the first DD region;

a second source/drain region in the second DD region, wherein the first DD region comprises a first top surface being substantially flat, the second DD region comprises a second top surface being substantially flat, and wherein the gate electrode does not have any portion directly over the first top surface of the first DD region and the second top surface of the second DD region;

a first dielectric spacer on a sidewall of the first DD region; and

a second dielectric spacer on a sidewall of the second DD region.

2. The integrated circuit structure of claim 1, wherein the first DD region, the second DD region, the first source/drain region, and the second source/drain region are of a first conductivity type, and wherein the HVW region is of a second conductivity type opposite the first conductivity type.

3. The integrated circuit structure of claim 1, wherein the bottom of the recess is higher than bottom surfaces of the first DD region and the second DD region.

4. The integrated circuit structure of claim 3, wherein the bottom of the recess is lower than bottom surfaces of the first source/drain region and the second source/drain region.

5. The integrated circuit structure of claim 1, wherein the recess comprises a first edge and a second edge opposing the first edge, and wherein the first edge is the sidewall of the first DD region, and the second edge is the sidewall of the second DD region.

6. The integrated circuit structure of claim 1, wherein the first and the second dielectric spacers are over the gate dielectric and the gate electrode.

7. The integrated circuit structure of claim 6, wherein each of the first and the second dielectric spacers comprises a portion vertically overlapping a portion of the gate dielectric.

8. The integrated circuit structure of claim 6, wherein-a-bottom surface of the first dielectric spacer contacts one of a top surface of the gate dielectric and a top surface of the gate electrode.

9. The integrated circuit structure of claim 1 further comprising a shallow trench isolation (STI) region in the semiconductor substrate, wherein the bottom of the recess is substantially level with a bottom of the STI region.

10. An integrated circuit structure comprising:

a semiconductor substrate;

a high-voltage well (HVW) region in the semiconductor substrate;

a first double diffusion (DD) region in the HVW region;

a recess extending from a top surface of the semiconductor substrate into a portion of the first DD region;

a gate dielectric extending into the recess;

a gate electrode over the gate dielectric; and

a first source/drain region in the first DD region, wherein substantially an entirety of the gate electrode is lower than a top surface of the first source/drain region.

11. The integrated circuit structure of claim 10 further comprising a dielectric spacer on an edge of the recess and over the gate electrode and the gate dielectric.

12. The integrated circuit structure of claim 11, wherein the dielectric spacer comprises a portion vertically overlapping a portion of the gate dielectric.

13. The integrated circuit structure of claim 10 further comprising:

a second DD region in the HVW region and spaced apart from the first DD region by a part of the HVW region; and

a second source/drain region in the second DD region.

14. The integrated circuit structure of claim 10 further comprising a shallow trench isolation (STI) region in the semiconductor substrate, wherein a bottom of the recess is substantially level with a bottom of the STI region.

15. The integrated circuit structure of claim 10, wherein the first DD region and the first source/drain region are of a first conductivity type, and wherein the HVW region is of a second conductivity type opposite the first conductivity type.

16. The integrated circuit structure of claim 10, wherein a bottom of the recess is higher than a bottom surface of the first DD region.

17. An integrated circuit structure comprising:

a semiconductor substrate;

a shallow trench isolation (STI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate;

a high-voltage well (HVW) region in the semiconductor substrate;

a double diffusion (DD) region in the HVW region;

a recess extending from a top surface of the semiconductor substrate into a portion of the DD region, wherein a bottom of the recess is substantially level with a bottom of the STI region;

a gate dielectric extending into the recess;

a gate electrode over the gate dielectric and comprising a portion in the recess; and

a source/drain region in the DD region.

18. The integrated circuit structure of claim 17, wherein an entirety of the gate electrode is lower than a top surface of the STI region.

19. The integrated circuit structure of claim 17 further comprising a dielectric spacer comprising a portion in the recess and over the gate electrode, wherein an edge of the dielectric spacer contacts an edge of the DD region.

20. The integrated circuit structure of claim 19, wherein an entirety of the dielectric spacer is in the recess.