TEST CIRCUIT AND SYSTEM

• US 20110163760A1
• Filed: 01/06/2010
• Published: 07/07/2011
• Est. Priority Date: 01/06/2010
• Status: Active Grant

• Current Assignee: GE Infrastructure Technology, LLC (General Electric Company)
• Original Assignee: General Electric Company
• Inventors: ROUSE, ERIC WADE, KELLEY, PAUL DOUGLAS
• Granted Patent: US 7,969,171 B1
• Time in Patent Office: Days
• US Class Current: 324/555
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A test circuit and system for testing one or more electrical properties of an electronic circuit or other device under test (DUT) by applying and monitoring test signals to the DUT is disclosed. The test circuit can utilize a plurality of universal interface channel circuits in a single automated test system to provide a unique and flexible approach for testing electronic circuits or devices that has many advantages. A single data acquisition circuit can coupled to one or more universal interface channel circuits. Each of the universal interface channel circuits can be independently commanded by the data acquisition circuit to provide one of a variety of test signals to a DUT as desired.

Claims

1. A test circuit, comprising:

a data acquisition circuit configured to provide a first test signal;

a digital I/O device configured to provide a control signal and a second test signal; and

at least one channel circuit said channel circuit comprising

a first path configured to accommodate the first test signal;

a second path configured to accommodate the second test signal;

a test node; and

a switching device;

wherein said digital I/O device is coupled to the switching device such that said digital I/O device provides the control signal to said switching device to control said switching device to selectively couple one of said first path or said second path to said test node.

2. The test circuit of claim 1, wherein said first test signal comprises one of a digital input signal, a digital output signal, a static analog signal, an analog input signal, an analog output signal, an oscilloscope signal, a digital multimeter signal, a counter/timer signal, or a comparator signal.

3. The test circuit of claim 2, wherein the second test signal comprises one of a digital input signal, a digital output signal, a static analog signal, an analog input signal, an analog output signal, an oscilloscope signal, a digital multimeter signal, a counter/timer signal, or a comparator signal.

4. The test circuit of claim 1, wherein said data acquisition circuit is configured to control said digital I/O device.

5. The test circuit of claim 1, wherein said at least one channel circuit is located on a channel circuit board, said channel circuit board comprising a plurality of channel circuits.

6. The test circuit of claim 5, wherein said digital I/O device is configured to provide a different first test signal to each of said plurality of test circuits.

7. The test circuit of claim 6, wherein said data acquisition circuit is configured to provide the same second test signal to each of said plurality of test circuits.

8. A system, comprising:

a data acquisition circuit configured to provide a first test signal;

a channel circuit board coupled to said data acquisition circuit, said channel circuit board comprising a plurality of channel circuits and a plurality of I/O devices, wherein each of said plurality of I/O devices are configured to provide a second test signal to at least one of said plurality of channel circuits;

each said channel circuit comprising a first path configured to accommodate the first test signal, a second path configured to accommodate the second test signal, a test node, and a switching device configured to selectively couple one of said first path or said second path to said test node;

wherein each of said plurality of I/O devices is configured to control said switching device of at least one of said plurality of channel circuits.

11. The system of claim 8, wherein said data acquisition circuit is configured to control each of said plurality of I/O devices.

12. The system of claim 8, wherein said data acquisition circuit is coupled to a plurality of channel circuit boards.

9. (canceled)

10. The system of claim 9, wherein said data acquisition circuit is configured to provide the same first test signal to each of said plurality of channel circuits.

13. A test circuit, comprising:

a data acquisition circuit configured to provide a plurality of analog output signals through a plurality of first electrical contacts and to provide a plurality of analog input signals through a plurality of second electrical contacts;

a digital I/O device configured to provide a digital output signal and a digital input signal;

a digital to analog converter circuit configured to provide a static analog signal;

a plurality of channel circuits, each said channel circuit comprising a plurality of first paths coupled to said plurality of first electrical contacts, a plurality of second paths coupled to said plurality of second electrical contacts, a third path configured to accommodate the digital input signal, a fourth path configured to accommodate the digital output signal and the static analog signal, a switching device, and a test node;

wherein said switching device of each said channel circuit is configured to selectively couple one of said plurality of first paths, plurality of second paths, third path, or fourth path to said test node.

14. The test circuit of claim 13, wherein said switching device comprises a multiplexer.

15. The test circuit of claim 13, wherein said digital I/O device is configured to independently control said switching device of each said channel circuit.

16. The test circuit of claim 13, wherein said data acquisition circuit comprises a processor configured to control the plurality of analog output signals and the plurality of analog input signals provided by said data acquisition circuit.

17. The test circuit of claim 13, wherein said data acquisition circuit is configured to control the digital I/O device.

18. The test circuit of claim 13, wherein at least one of said plurality of channel circuits is used to perform a single ended digital multimeter or oscilloscope measurement.

19. The test circuit of claim 13, wherein said plurality of channel circuits comprises a first channel circuit and a second channel circuit, said first channel circuit being configured to operate as a positive path for a differential digital multimeter or oscilloscope measurement and said second channel circuit being configured to operate as a negative path for a differential digital multimeter or oscilloscope measurement

20. The test circuit of claim 13, wherein said plurality of channel circuits comprises a first channel circuit, a second channel circuit and a third channel circuit, said first channel circuit configured to accommodate a first leg of a three phase waveform, the second channel circuit configured to accommodate a second leg of the three phase waveform, and the third channel configured to accommodate a third leg of the three phase waveform.