METHOD AND APPARATUS FOR IDENTIFYING CONNECTIONS BETWEEN CONFIGURABLE NODES IN A CONFIGURABLE INTEGRATED CIRCUIT

• US 20110163781A1
• Filed: 11/30/2010
• Published: 07/07/2011
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Andre Rohe, Steve Teig
• Inventors: Rohe, Andre, Teig, Steven
• Granted Patent: US 8,281,273 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Abstract

Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.

Claims

1-20. -20. (canceled)

21. An integrated circuit (“

IC”

) comprising;

a plurality of configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of connection schemes for the plurality of configurable nodes in the array, wherein a connection scheme is an arrangement of connections between configurable nodes,

wherein each connection scheme for a particular configurable node specifies (i) a set of connections between the particular configurable node and a plurality of closest aligned configurable nodes in the array and (ii) a plurality of long offset direct connections, wherein the connections in the connection scheme do not include intervening interconnect circuits.

22. The IC of claim 21, wherein the connection scheme comprises a first set of connections that has a symmetrical relationship with a second set of connections in the connection scheme.

23. The IC of claim 21, wherein a first connection in the connection scheme is rotationally related to a second connection in the connection scheme.

24. The IC of claim 21, wherein a long offset connection is a connection between two configurable nodes that are not in the same row and column and that are separated by at least two rows or two columns.

25. The IC of claim 21, wherein at least one connection in the connection scheme is between configurable nodes that are in the same row or same column.

26. The IC of claim 25, wherein at least one connection in the connection scheme connects offset and aligned configurable nodes.

27. The IC of claim 21, wherein each of the plurality of connection schemes has connections between offset and aligned configurable nodes.

28. The IC of claim 21, wherein a connection is defined by a set of wire segments.

29. The IC of claim 28, wherein a connection further includes a buffer circuit.

30. The IC of claim 28, wherein at least one set of wire segments includes at least two wire segments on at least two different wiring layers of the IC.

31. The IC of claim 30, wherein the set of wire segments with at least two wires includes a set of vias that connect the wire segments.

33. The IC of claim 21, wherein two configurable nodes of a same type have different connection schemes, wherein two configurable nodes are of the same type when they one or more identical configurable circuit elements.

32. (canceled)

34. An electronic device comprising:

an integrated circuit (“

IC”

), the IC comprising;

a plurality of configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of connection schemes for the plurality of configurable nodes in the array, wherein a connection scheme is an arrangement of connections between configurable nodes,

wherein each connection scheme for a particular configurable node specifies (i) a set of connections between the particular configurable node and a plurality of closest aligned configurable nodes in the array and (ii) a plurality of long offset direct connections, wherein the connections in the connection scheme do not include intervening interconnect circuits; and

a memory device that stores configuration data for programming the configurable nodes in the IC.

35. The IC of claim 34, wherein the connection scheme comprises a first set of connections that has a symmetrical relationship with a second set of connections in the connection scheme.

36. The IC of claim 34, wherein a first connection in the connection scheme is rotationally related to a second connection in the connection scheme.

37. The IC of claim 34, wherein a long offset connection is a connection between two configurable nodes that are not in the same row and column and that are separated by at least two rows or two columns.

38. The IC of claim 34, wherein at least one connection in the connection scheme is between configurable nodes that are in the same row or same column.

39. The IC of claim 34, wherein two configurable nodes of the a same type have different connection schemes, wherein two configurable nodes are of the same type when they one or more identical configurable circuit elements.