POWER SWITCH WITH REVERSE CURRENT BLOCKING CAPABILITY

• US 20110163797A1
• Filed: 06/30/2010
• Published: 07/07/2011
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Decicon Incorporated
• Original Assignee: Decicon Incorporated
• Inventors: Posat, Baris
• Granted Patent: US 8,508,078 B2
• Time in Patent Office: Days
• US Class Current: 327/537
• CPC Class Codes: H02H 3/18 responsive to reversal of direct current
• CPC Class Codes: H02J 7/0034 using reverse polarity correcting or protecting circuits mechanical means of polarity protection H02J7/0045
• CPC Class Codes: H02J 7/0036 using connection detecting circuits H02J7/0034 takes precedence
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/302 in field-effect transistor switches
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2017/307 circuits simulating a diode, e.g. threshold zero

Abstract

A switching circuit controls the flow of current between its input and output in accordance with the state of a control signal applied to the circuit. When the control signal is in a first state and the voltage applied to the input is higher than the voltage at the output, the circuit provides a low resistance path between its input and output terminals thereby enabling current to flow from the input to the output. When the control signal is in the first state and the voltage at the output is higher than the voltage at the input, the circuit inhibits current flow from the output to the input. When the control signal is in a second state, the circuit is turned off thus inhibiting current flow between the input and the output.

Claims

1. A reverse current blocking (RCB) circuit comprising:

a first transistor having a first current carrying terminal coupled to a first input terminal of the RCB circuit and a second current carrying terminal coupled to a first node;

a first charge pump operative to supply a first voltage signal to a gate terminal of the first transistor in response to a reference voltage;

a second transistor having a first current carrying terminal coupled to an output terminal of the RCB circuit, and a second current carrying terminal coupled to the first node;

a second charge pump operative to supply a second voltage signal to a gate terminal of the second transistor in response to a feedback signal; and

an amplifier having a first input terminal receiving the output voltage of the RCB circuit, and a second input terminal receiving a voltage defined by a voltage of the first node and an offset voltage, said amplifier supplying the feedback signal to the second charge pump.

2. The (RCB) circuit of claim 1 further comprising:

a current sensing circuit operative to sense a current flowing through the first input terminal of the RCB circuit; and

a current sink block adapted to sink current from the gate terminal of the first transistor when the sensed current exceeds a predefined value.

3. The (RCB) circuit of claim 2 wherein said current sink is a non-linear current sink.

4. The RCB circuit of claim 1 wherein said first and second transistors are N-channel MOS (NMOS) transistors, wherein the body-to-source diodes of the first and second NMOS transistors form back-to-back diodes.

5. The RCB circuit of claim 1 wherein said second charge pump comprises:

a first multiplier circuit operative to receive first and second non-overlapping pulse signals varying in voltage level between first and second supply voltages, and in response, generating third and fourth non-overlapping signals varying in voltage level between the first supply voltage and a multiple of the second supply voltage;

a second multiplier circuit operative to generate a third voltage signal that is the multiple of the feedback voltage in response to the first multiplier circuit and further in response to the first non-overlapping pulse signal and to fifth and sixth non-overlapping pulse signals, said fifth non-overlapping pulse signal being an inverse of the first non-overlapping pulse signal, and said sixth non-overlapping pulse signal being an inverse of the second non-overlapping pulse signal;

a third multiplier circuit operative to generate a fourth voltage signal that is the multiple of the feedback voltage in response to the first multiplier circuit and further in response to the second, fifth and sixth non-overlapping pulse signals; and

a coupling circuit responsive to the second and third multiplier circuit as well as to the first, second, fifth, and sixth non-overlapping pulse signals so as to generate the second voltage signal.

6. The RCB circuit of claim 5 wherein said multiple is two.

7. The RCB circuit of claim 6 wherein said first, second, fifth and sixth non-overlapping pulse signals are generated by a non-overlapping clock generation circuit and in response to a clock signal internally generated or externally supplied.

8. The RCB circuit of claim 6 wherein said third multiplier circuit comprises:

a first transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the third non-overlapping pulse signal, and a drain terminal coupled to a first terminal of a first capacitive element, said first transistor being an NMOS transistor;

a second transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the second non-overlapping pulse signal, and a drain terminal coupled to a second terminal of the first capacitive element, said second transistor being a PMOS transistor;

a third transistor having a drain terminal receiving the feedback voltage, a gate terminal receiving the sixth non-overlapping pulse signal, and a source terminal coupled to the second terminal of the first capacitive element, said third transistor being an NMOS transistor;

a fourth transistor having a drain terminal coupled to the second terminal of the first capacitive element, a source terminal coupled to first supply voltage, and a gate terminal receiving the fifth non-overlapping pulse signal, said fourth transistor being an NMOS transistor;

a fifth transistor having a source terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving the feedback voltage, and a drain terminal supplying the fourth voltage signal;

said fifth transistor being a PMOS transistor;

a sixth transistor having a drain terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving the fourth non-overlapping pulse signal, and a source terminal supplying the fourth voltage signal;

said sixth transistor being an NMOS transistor; and

a seventh transistor having a drain terminal supplying the fourth voltage signal, a source terminal coupled to first supply voltage, and a gate terminal receiving the fifth non-overlapping pulse signal, said seventh transistor being an NMOS transistor.

9. The RCB circuit of claim 8 wherein said second multiplier circuit comprises:

a first transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the fourth non-overlapping pulse signal, and a drain terminal coupled to a first terminal of a second capacitive element, said first transistor being an NMOS transistor;

a second transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the first non-overlapping pulse signal, and a drain terminal coupled to a second terminal of the second capacitive element, said second transistor being a PMOS transistor;

a third transistor having a drain terminal receiving the feedback voltage, a gate terminal receiving the fifth non-overlapping pulse signal, and a source terminal coupled to the second terminal of the second capacitive element, said third transistor being an NMOS transistor;

a fourth transistor having a drain terminal coupled to the second terminal of the second capacitive element, a source terminal coupled to the first supply voltage, and a gate terminal receiving the sixth non-overlapping pulse signal, said fourth transistor being an NMOS transistor;

a fifth transistor having a source terminal coupled to the first terminal of the second capacitive element, a gate terminal receiving the feedback voltage, and a drain terminal supplying the third voltage signal;

said fifth transistor being a PMOS transistor;

a sixth transistor having a drain terminal coupled to the first terminal of the second capacitive element, a gate terminal receiving the third non-overlapping pulse signal, and a source terminal supplying the third voltage signal;

said sixth transistor being an NMOS transistor; and

a seventh transistor having a drain terminal supplying the third voltage signal, a source terminal coupled to first supply voltage, and a gate terminal receiving the sixth non-overlapping pulse signal, said seventh transistor being an NMOS transistor.

10. The RCB circuit of claim 9 wherein said first supply voltage is the ground voltage.

11. The RCB circuit of claim 10 wherein said first multiplier circuit comprises:

a first transistor having a source terminal receiving the ground voltage, a gate terminal receiving the first non-overlapping pulse signal, and a drain terminal supplying the third non-overlapping pulse signal, said first transistor being an NMOS transistor;

a second transistor having a source terminal coupled to first terminal of a first capacitive element, a gate terminal receiving the first reference voltage, and a drain terminal supplying the third non-overlapping pulse signal, said second transistor being a PMOS transistor;

a third transistor having a drain terminal receiving the first reference voltage, a gate terminal coupled to a first terminal of a second capacitive element, and a source terminal coupled to the first terminal of the first capacitive element, said third transistor being an NMOS transistor, said second terminal of the first capacitive element receiving an inverse of the first non-overlapping pulse signal;

a fourth transistor having a drain terminal receiving the first reference voltage, a gate terminal coupled to the first terminal of the first capacitive element, and a source terminal coupled to the first terminal of the second capacitive element, said fourth transistor being an NMOS transistor;

a fifth transistor having a source terminal coupled to the first terminal of the second capacitive element, a gate terminal receiving the first reference voltage, and a drain terminal supplying the fourth non-overlapping pulse signal, said fifth transistor being a PMOS transistor;

a sixth transistor having a drain terminal supplying the third non-overlapping pulse signal, a gate terminal receiving the second non-overlapping pulse signal, and a source terminal receiving the ground voltage;

said sixth transistor being an NMOS transistor, said second terminal of the second capacitive element receiving an inverse of the second non-overlapping pulse signal.

12. The RCB circuit of claim 11 wherein said coupling circuit comprises:

a first transistor having a source terminal supplying the second voltage signal, a drain terminal coupled to a first terminal of a first capacitive element, and a gate terminal coupled to a first terminal of a second capacitive element, said first transistor being a PMOS transistor, said second terminal of the first capacitive element receiving the fourth voltage signal, and said second terminal of the second capacitive element receiving the second non-overlapping pulse signal;

a second transistor having a drain terminal coupled to the first terminal of the first capacitive element, a source terminal coupled to the first node, and a gate terminal coupled to a second terminal of a third capacitive element, said second transistor being an NMOS transistor;

a third transistor having a source terminal supplying the second voltage signal, a drain terminal coupled to the first terminal of the second capacitive element, and a gate terminal coupled to a first terminal of a fourth capacitive element, said third transistor being a PMOS transistor, the second terminal of the second capacitive element receiving the second non-overlapping pulse signal;

a fourth transistor having a drain terminal coupled to the second terminal of the third capacitive element, a source terminal coupled to the first node, and a gate terminal coupled to a second terminal of a fifth capacitive element, said fourth transistor being an NMOS transistor, the first terminal of the fourth capacitive element receiving the fifth non-overlapping pulse signal;

a fifth transistor having a source terminal supplying the second voltage signal, a drain terminal coupled to the first terminal of the fourth capacitive element, and a gate terminal coupled to the first terminal of the second capacitive element, said fifth transistor being a PMOS transistor, the second terminal of the fourth capacitive element receiving the first non-overlapping pulse signal;

a sixth transistor having a drain terminal coupled to the second terminal of the fifth capacitive element, a source terminal coupled to the first node, and a gate terminal coupled to the second terminal of the third capacitive element, said fourth transistor being an NMOS transistor, the first terminal of the fifth capacitive element receiving the sixth non-overlapping pulse signal;

a seventh transistor having a source terminal supplying the second voltage signal, a drain terminal coupled to a first terminal of a sixth capacitive element, and a gate terminal coupled to the first terminal of the fourth capacitive element, said seventh transistor being a PMOS transistor, said second terminal of the sixth capacitive element receiving the third voltage signal;

an eight transistor having a drain terminal coupled to the first terminal of the sixth capacitive element, a source terminal coupled to the first node, and a gate terminal coupled to the second terminal of the fifth capacitive element, said second transistor being an NMOS transistor, said second terminal of the sixth capacitive element receiving the third voltage signal.

13. The RCB circuit of claim 2 wherein said non-linear current sink block is an exponential current sink block.

14. The RCB circuit of claim 1 wherein said offset voltage is an inherent offset voltage present in the amplifier.

15. The RCB circuit of claim 1 wherein said offset voltage is supplied by a component external to the amplifier.

16. A circuit comprising:

a charge pump adapted to supply current to a gate terminal of an MOS transistor;

a current sense circuit adapted to sense a current flowing through a drain terminal of the MOS transistor and to generate a sense signal in response; and

a discharge circuit adapted to discharge current from the gate terminal of the MOS transistor, said discharge current being defined by a difference between the sense signal and a reference signal such that the discharge current increases non-linearly as said difference increases and said discharge current decrease non-linearly when said difference decreases.

17. The circuit of claim 16 wherein said discharge current is non-linearly dependent on the difference between the sense signal and the reference signal.

18. The circuit of claim 17 wherein said discharge current is exponentially dependent on the difference between the sense signal and the reference signal.

19. A switching circuit comprising:

first and second transistors disposed between input and output terminals of the switching circuit;

a first voltage multiplier generating a first intermediate signal that is a multiple of an analog feedback signal in response to a first phase of a clock signal, said first analog signal having a range defined by first and second supply voltages;

a second voltage multiplier generating a second intermediate signal that is a multiple of the analog feedback signal in response to a second non-overlapping phase of the clock signal; and

a coupling circuit selectively applying one of the intermediate signals in response to opposite phases of the clock signal to a pair of terminals of at least one of the first and second transistors so as maintain conductive path between the input and output terminals of the switching circuit when the voltage of the input terminal is higher than the voltage of the output terminal, and further to turn off the conduction path between the input and output terminals of the switching circuit when the voltage of the input terminal is smaller than the voltage of the output terminal.

20. Two voltage multipliers clocked by opposite phases of a clock signal, each multiplying an analog input signal changing between the ground and a supply voltage level by a predefined multiplication factor and generating two intermediate signals;

and

a coupler circuit selectively coupling each one of the intermediate signals on opposite phases of the clock signal between two output terminals, thereby maintaining a continuous-time signal path from the input to the output.

21. A multiplier circuit comprising:

a first transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the third non-overlapping pulse signal, and a drain terminal coupled to a first terminal of a first capacitive element, said first transistor being an NMOS transistor;

a second transistor having a source terminal receiving the feedback voltage, a gate terminal receiving the second non-overlapping pulse signal, and a drain terminal coupled to a second terminal of the first capacitive element, said second transistor being a PMOS transistor;

a third transistor having a drain terminal receiving the feedback voltage, a gate terminal receiving the sixth non-overlapping pulse signal, and a source terminal coupled to the second terminal of the first capacitive element, said third transistor being an NMOS transistor;

a fourth transistor having a drain terminal coupled to the second terminal of the first capacitive element, a source terminal coupled to first supply voltage, and a gate terminal receiving the fifth non-overlapping pulse signal, said fourth transistor being an NMOS transistor;

a fifth transistor having a source terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving the feedback voltage, and a drain terminal supplying the fourth voltage signal;

said fifth transistor being a PMOS transistor;

a sixth transistor having a drain terminal coupled to the first terminal of the first capacitive element, a gate terminal receiving the fourth non-overlapping pulse signal, and a source terminal supplying the fourth voltage signal;

said sixth transistor being an NMOS transistor; and

a seventh transistor having a drain terminal supplying the fourth voltage signal, a source terminal coupled to first supply voltage, and a gate terminal receiving the fifth non-overlapping pulse signal, said seventh transistor being an NMOS transistor.