ARRANGEMENT FOR UTILIZATION RATE DISPLAY AND METHODS THEREOF
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Accused Products
Abstract
A network arrangement for automatically displaying statistical data is provided. The arrangement includes a port for receiving data traffic, a physical interface layer for copying data traffic, and a bus for directing a copy of the data traffic to monitoring devices. The arrangement also includes logic arrangement for analyzing the copy of data traffic, which includes at least a Receive Data Valid signal (including a rising edge and a falling edge) and a Receive Clock signal (including a rising edge and a falling edge). The arrangement further includes incrementing a first counter when the Receive Data Valid rising edge is received and incrementing a second counter when at least one of the Receive Clock rising edge and the Receive Clock falling edge is received. The arrangement moreover includes logic arrangement for displaying statistical data pertaining to the data traffic and a visual display arrangement for displaying statistical data.
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Citations
44 Claims
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1-24. -24. (canceled)
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25. A network arrangement for automatically displaying statistical data on a network device, comprising:
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a set of input ports for receiving data traffic, wherein said set of input ports including at least a first port; a physical interface layer (PHY) configured for copying said data traffic; a bus configured for directing a copy of said data traffic to a set of monitoring devices; a first logic arrangement for analyzing said copy of said data traffic, wherein said data traffic including a plurality of signals, wherein said plurality of signals including at least a Receive Data Valid signal;
wherein said Receive Data Valid signal including a Receive Data Valid rising edge and a Receive Data Valid falling edge, anda Receive Clock signal, wherein said Receive Clock signal including a Receive Clock rising edge and a Receive Clock falling edge, said Receive Clock rising edge being a first byte of data and said Receive Clock falling edge being a second byte of data; a first counter configured to be incremented by one when said Receive Data Valid rising edge is received, said Receive Data Valid rising edge indicating a valid data packet; a second counter configured to be incremented by one when at least one of said Receive Clock rising edge and said Receive Clock falling edge is received; a second logic arrangement for displaying said statistical data pertaining to said data traffic; and a visual display arrangement being configured to display said statistical data. - View Dependent Claims (26, 27, 28, 29, 32, 33, 34, 35, 36)
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- 30. The network arrangement of claim 30 wherein said FPGA is configured to correlate said Receive Data Valid signal to said Receive Clock signal to determine number of bytes in said valid data packet.
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37. A method for automatically displaying statistical data on a visual display arrangement of a network device, comprising:
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receiving a first data packet at a first port of a set of input network ports, wherein said first port including a first counter and a second counter; copying said first data packet; utilizing a bus to direct a copy of said first data packet to a set of monitoring devices, wherein said bus is associated with said first port; extracting a plurality of signals from said bus, wherein said plurality of signals including at least a Receive Data Valid signal, wherein said Receive Data Valid signal including a Receive Data Valid rising edge and a Receive Data Valid falling edge, and a Receive Clock signal, wherein said Receive Clock signal including a Receive Clock rising edge and a Receive Clock falling edge, said Receive Clock rising edge being a first byte of data and said Receive Clock falling edge being a second byte of data; incrementing said first counter by one when said Receive Data Valid rising edge is received, said Receive Data Valid rising edge indicating a valid data packet; incrementing said second counter by one when at least one of said Receive Clock rising edge and said Receive Clock falling edge is received; correlating data collected by said first counter and said second counter to calculate said statistical data; and displaying said statistical data on said visual display arrangement of said network device. - View Dependent Claims (38, 42, 43, 44)
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- 39. The method of 38 wherein a field-programmable field array (FPGA) is configured to perform analysis of said Receive Data Valid signal and said Receive Clock signal to determine a utilization rate of said network device, said utilization rate being said network device throughput.
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42-1. The method of claim 37 wherein displaying said statistical data includes periodically updating said statistical data to display real-time data.
Specification