THREE-STAGE ARCHITECTURE FOR ADAPTIVE CLOCK RECOVERY
First Claim
1. An adaptive clock recovery (ACR) system (e.g., 100) for a receiver, the ACR system comprising:
- a first closed-loop control processor (e.g., 202) that generates a reference phase signal (e.g., 124) from an input phase signal (e.g., 112) representing packet delay values (e.g., D(i)) corresponding to arrival times of packets at the receiver;
a delay-offset estimation component (e.g., 204) that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal (e.g., 206) representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal;
a delay-offset compensation component (e.g., 210) that generates a delay-offset-compensated phase signal (e.g., 212) based on the reference phase signal and the delay-offset estimate signal; and
a second closed-loop control processor (e.g., 214) that generates, from the delay-offset-compensated phase signal, an output phase signal (e.g., 122) that can be used to generate a recovered clock signal.
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Accused Products
Abstract
An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to generate offset-compensated phase values corresponding to the delay-floor. The ACR system also has a second closed-loop control processor (e.g., a second PI processor) that smoothes the offset-compensated phase values to generate an output phase signal that can be used to generate a relatively phase stable recovered clock signal, even during periods of varying network load that adversely affect the uniformity of the packet arrival times.
9 Citations
12 Claims
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1. An adaptive clock recovery (ACR) system (e.g., 100) for a receiver, the ACR system comprising:
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a first closed-loop control processor (e.g., 202) that generates a reference phase signal (e.g., 124) from an input phase signal (e.g., 112) representing packet delay values (e.g., D(i)) corresponding to arrival times of packets at the receiver; a delay-offset estimation component (e.g., 204) that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal (e.g., 206) representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal; a delay-offset compensation component (e.g., 210) that generates a delay-offset-compensated phase signal (e.g., 212) based on the reference phase signal and the delay-offset estimate signal; and a second closed-loop control processor (e.g., 214) that generates, from the delay-offset-compensated phase signal, an output phase signal (e.g., 122) that can be used to generate a recovered clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An adaptive clock recovery (ACR) system (e.g., 100) for a receiver, the ACR system comprising:
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a first closed-loop control processor (e.g., 202) that generates a reference phase signal (e.g., 124) from an input phase signal (e.g., 112) representing packet delay values (e.g., D(i)) corresponding to arrival times of packets at the receiver; a delay-offset estimation component (e.g., 204) that compares the input phase signal to the reference phase signal to generate a delay-offset estimate signal (e.g., 206) representative of an established phase offset for the packet arrival times relative to the reference phase signal; a delay-offset compensation component (e.g., 210) that generates a delay-offset-compensated phase signal (e.g., 212) based on the reference phase signal and the delay-offset estimate signal; and a second closed-loop control processor (e.g., 214) that generates, from the delay-offset-compensated phase signal, an output phase signal (e.g., 122) that can be used to generate a recovered clock signal.
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12. A method for recovering a clock signal in a packet system, the method comprising:
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generating a reference phase signal (e.g., 124) from an input phase signal (e.g., 112) representing packet delay values (e.g., D(i)) corresponding to arrival times of packets at a receiver; comparing the input phase signal to the reference phase signal generating a delay-offset estimate signal (e.g., 206) representative of a delay-floor phase offset for the packet arrival times relative to the reference phase signal; generating a delay-offset-compensated phase signal (e.g., 212) based on the reference phase signal and the delay-offset estimate signal; and generating, from the delay-offset-compensated phase signal, an output phase signal (e.g., 122) that can be used to generate a recovered clock signal.
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Specification