DIGITAL PLL CIRCUIT AND COMMUNICATION DEVICE

• US 20110164675A1
• Filed: 03/16/2011
• Published: 07/07/2011
• Est. Priority Date: 10/23/2008
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: SENOUE, Fumiaki, Okamoto, Kouji
• Granted Patent: US 8,780,974 B2
• Time in Patent Office: Days
• US Class Current: 375/240.01
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.

Claims

1. A digital PLL circuit receiving a reference signal and outputting a clock signal with a frequency obtained by multiplying a frequency of the reference signal by a value indicating a predetermined magnification ratio and containing an integer portion and a fractional portion, the circuit comprising:

a controlled oscillator configured to receive a control amount and change the frequency of the clock signal output from the digital PLL circuit in accordance with the received control amount;

a first counter configured to count the clock signal with the frequency changed by the controlled oscillator;

a second counter configured to increment the predetermined magnification ratio in response to a retiming signal obtained by retiming the reference signal with the clock signal from the controlled oscillator;

a comparator configured to compare a count value of the first counter to an integer portion of a count value of the second counter and output the difference as a phase error of the integer portion;

a minute phase error generator configured to generate a plurality of threshold values close to an amplitude value of the reference signal based on the fractional portion of the count value of the second counter, detect the amplitude value of the reference signal based on the plurality of threshold values, and generate minute phase error information as a phase error of the fractional portion between the reference signal and the output clock signal from the controlled oscillator based on the detected amplitude value;

a filter section configured to receive the phase error of the integer portion from the comparator and the minute phase error information as the phase error of the fractional portion from the minute phase error generator, and smooth a sum of the two phase errors; and

a control amount generator configured to generate and output the control amount for the controlled oscillator based on an output of the filter section.

2. The digital PLL circuit of claim 1, wherein

the minute phase error generator includes

a plurality of threshold banks, each configured to output a plurality of threshold values,

a selection section configured to receive the fractional portion of the count value of the second counter, and select one of the plurality of threshold banks based on the fractional portion, and

a plurality of comparators provided in number equal to the number of the threshold values output from the threshold bank selected by the selection section, and configured to receive the corresponding threshold values from the selected threshold bank, receive the reference signal, and compare the reference signal to the received threshold values.

3. The digital PLL circuit of claim 1, wherein

the minute phase error generator detects amplitude values of the reference signal a plurality of times based on the generated plurality of threshold values, and generates minute phase error information as a phase error of the fractional portion between the reference signal and the output clock signal from the controlled oscillator based on a maximum value, a minimum value, and an amplitude value just before the second counter increments the predetermined magnification ratio out of the detected plurality of amplitude values, and the predetermined magnification ratio containing the integer portion and the fractional portion.

4. The digital PLL circuit of claim 3, wherein

the minute phase error generator detects the amplitude value just before the second counter increments the predetermined magnification ratio at thinning of the clock signal output from the digital PLL circuit in accordance with an output of the first counter and an output of the second counter.

5. The digital PLL circuit of claim 3, wherein

the minute phase error generator switches the plurality of threshold banks and detects the maximum value and the minimum value of the amplitude values of the reference signal when the PLL circuit is in transition to normal operation or in a learning mode, and normalizes the minute phase error using the detected maximum and minimum values in the normal operation after the transition.

6. The digital PLL circuit of claim 1, wherein

the count value of the first counter and the count value of the second counter are held in two respective register circuits synchronized with the retiming signal, and

the comparator compares the count value of the first counter held in one of the two register circuits to the integer portion of the count value of the second counter held in the other register circuit.

7. The digital PLL circuit of claim 1, wherein

the control amount generation section outputs to the controlled oscillator, a result of modulating a part or whole of the control amount for the controlled oscillator as a control amount.

8. The digital PLL circuit of claim 1, wherein

the controlled oscillator includes a digital-to-analog converter and a voltage controlled oscillator.

9. The digital PLL circuit of claim 1, wherein

the controlled oscillator is a digital controlled oscillator.

10. The digital PLL circuit of claim 1, wherein

the reference signal has a waveform equivalent to a sine wave.

11. The digital PLL circuit of claim 1, wherein

the reference signal has a sowtooth waveform.

12. A communication device comprising:

an LSI including a signal processing circuit configured to decode a received signal containing sound data or video data with a clock signal obtained by using the digital PLL circuit of claim 1; and

a display terminal configured to receive the decoding signal from the LSI, and display the decoded sound data or the decoded video data.