×

INTERFACE CIRCUIT

  • US 20110164693A1
  • Filed: 03/14/2011
  • Published: 07/07/2011
  • Est. Priority Date: 03/25/2009
  • Status: Abandoned Application
First Claim
Patent Images

1. An interface circuit for transmitting data bi-directionally between a host device and a sub device, comprising:

  • a first LSI mounted on the host device; and

    a second LSI mounted on the sub device, whereinthe first LSI has;

    a first clock generating circuit for generating a first transmission clock signal and a first reception clock signal separately in accordance with a first reference clock signal, and for generating a second reference clock signal for the sub device in accordance with the first reference clock signal;

    a differential driver for converting the second reference clock signal into a differential clock signal, to output the differential clock signal to the sub device;

    a first transmitting circuit block for converting parallel data into a first differential serial signal by using the first transmission clock signal, to output the first differential serial signal to the sub device; and

    a first receiving circuit block for receiving a second differential serial signal from the sub device, to convert the second differential serial signal into parallel data by using the first reception clock signal, after adjusting timing of the second differential serial signal, andthe second LSI has;

    a differential receiver for receiving the differential clock signal from the host device, to convert the differential clock signal into a third reference clock signal;

    a second clock generating circuit for generating a second transmission clock signal and a second reception clock signal separately in accordance with the third reference clock signal;

    a second transmitting circuit block for converting parallel data into a third differential serial signal by using the second transmission clock signal, to output the third differential serial signal to the host device; and

    a second receiving circuit block for receiving a fourth differential serial signal from the host device, to convert the fourth differential serial signal into parallel data by using the second reception clock signal, after adjusting timing of the fourth differential serial signal.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×