MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES

• US 20110165744A1
• Filed: 03/17/2011
• Published: 07/07/2011
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 8,227,305 B2
• Time in Patent Office: Days
• US Class Current: 438/241
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.

Claims

1. A method of fabricating a memory array comprising:

forming a plurality of conductive data/bit lines extending generally in a first direction in an upper surface of a semiconductive substrate;

forming a plurality of access transistors extending generally upward from the upper surface of the substrate and aligned generally atop a corresponding data/bit line, wherein forming the access transistors comprises;

forming a pillar extending generally upward from the upper surface of the substrate and generally aligned atop the corresponding data/bit line;

forming a source region generally at a lower portion of the pillar so as to be in electrical communication with the corresponding data/bit line;

forming a drain region generally at an upper portion of the pillar, wherein the pillar intermediate the source and drain regions is substantially fully depleted; and

forming a gate structure substantially about the pillar in lateral directions such that the access transistors are substantially off with no applied gate potential; and

forming a plurality of conductive word lines extending generally in a second direction and in electrical contact with a corresponding gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated about the corresponding pillar via the gate structure.

2. The method of claim 1 further comprising heavily doping regions of the upper surface of the substrate.

3. The method of claim 1, wherein the pillar has a generally rectangular horizontal cross-section.

4. The method of claim 1 further comprising forming the source regions substantially across the lower portion of the pillar.

5. The method of claim 1 further comprising arranging the second direction generally perpendicular to the first direction such that the data/bit lines and word lines with the corresponding access transistors define a generally rectangular array.

6. The method of claim 5 further comprising configuring the upper portion of the pillars with the drain regions for electrical connection to external circuit components.

7. The method of claim 6 further comprising interconnecting the upper portions of the pillars to a corresponding plurality of storage capacitor contacts such that the array defines a dynamic random access memory (DRAM) array.

8. The method of claim 1 further comprising:

associating a pair of conductive word lines with each corresponding access transistor; and

arranging the pair of word lines such that a first word line contacts the corresponding gate structure at the first surface and a second word line contacts the corresponding gate structure at an opposed second surface.

9. The method of claim 1, wherein forming the gate structure comprises forming the gate structure substantially surrounding a portion of the pillar.

10. The method of claim 1, wherein forming the gate structure comprises forming the gate structure along the entire vertical extent of the pillar.

11. A method of fabricating a memory array comprising:

forming a plurality of access transistors extending generally upward from an upper surface of a semiconductor substrate and aligned in association with a corresponding data/bit line, wherein forming the access transistors comprises;

forming a pillar;

forming a source region generally at a lower portion of the pillar so as to be in electrical communication with the corresponding data/bit line;

forming a drain region generally at an upper portion of the pillar, wherein at least a portion of the pillar intermediate the source and drain regions is depleted; and

forming a gate structure substantially about the pillar such that the access transistors are substantially off with no applied gate potential; and

forming a plurality of conductive word lines, each of the conductive word lines in electrical contact with a corresponding gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated about the corresponding pillar via the gate structure.

12. The method of claim 11 further comprising heavily doping regions of the upper surface of the substrate, wherein a plurality of data/bits lines comprise the heavily doped regions.

13. The method of claim 11, wherein the pillar has a generally rectangular horizontal cross-section.

14. The method of claim 11 further comprising forming the source regions so as to extend substantially across the lower portion of the pillar.

15. The method of claim 11 further comprising:

forming the data/bit lines in a first direction;

forming the plurality of conductive word lines in a second direction; and

arranging the second direction generally perpendicular to the first direction such that the data/bit lines and word lines with the corresponding access transistors define a generally rectangular array.

16. The method of claim 15 further comprising configuring the upper portion of the pillars with the drain regions for electrical connection to external circuit components.

17. The method of claim 16 further comprising interconnecting the upper portions of the pillars to a corresponding plurality of storage capacitor contacts such that the array defines a dynamic random access memory (DRAM) array.

18. The method of claim 11 further comprising:

associating a pair of conductive word lines with each corresponding access transistor; and

arranging the pair of word lines such that a first word line contacts the corresponding gate structure at the first surface and a second word line contacts the corresponding gate structure at an opposed second surface.

19. The method of claim 11, wherein forming the gate structure comprises forming the gate structure substantially surrounding a portion of the pillar.

20. The method of claim 11, wherein forming the gate structure comprises forming the gate structure along the entire vertical extent of the pillar.