METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS

• US 20110165771A1
• Filed: 02/07/2011
• Published: 07/07/2011
• Est. Priority Date: 04/11/2000
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Sheppard, Scott Thomas, Hagleitner, Helmut, Ring, Zoltan
• Granted Patent: US 8,202,796 B2
• Time in Patent Office: Days
• US Class Current: 438/609
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/445 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.

Claims

1. A method of forming conductive paths to electrical contacts of transistors in an integrated circuit without the need for wire bonding, comprising:

placing a transparent layer on a substrate surface that is opposite the electrical contacts;

masking the transparent layer with a photoresist to define via locations that are aligned with the electrical contacts;

etching through the transparent layer within a region defined by the mask with a first reactive ion etch; and

etching a via through a silicon carbide substrate of a transistor to each respective source, gate, and drain contact on an epitaxial layer of a transistor, in which the epitaxial layer is formed of a material other than silicon carbide, the source and drain contacts are formed from material that exhibits ohmic behavior when placed on the epitaxial layer, and the gate contact is formed of material that exhibits rectifying behavior when placed on the epitaxial layer, and wherein etching the via to the source, gate, and drain contacts comprises the steps of etching the silicon carbide substrate using an etchant that removes silicon carbide but does not remove the epitaxial layer so that the etching of the silicon carbide substrate stops at the epitaxial layer and thereafter etching the epitaxial layer using an etchant that removes the epitaxial layer but does not remove silicon carbide or the materials forming the source, gate, and drain contacts so that etching the epitaxial layer stops at the source, gate, and drain contacts.

2. A method of fabricating a transistor according to claim 1 wherein the transparent layer is indium-tin-oxide.

3. A method of fabricating a transistor according to claim 1 wherein the transparent layer is magnesium oxide.

4. A method of fabricating a transistor according to claim 1 wherein the first reactive ion etch uses chlorine.

5. A method of fabricating a transistor according to claim 1 wherein:

the step of etching the silicon carbide substrate comprises etching within the region defined by the mask with an inductively coupled plasma; and

the step of etching the epitaxial layer comprises etching within the region defined by the mask with a second reactive ion etch.

6. A method of fabricating a transistor according to claim 5 wherein:

the inductively coupled plasma etching step is carried out using sulfur hexafluoride as the etchant; and

the second reactive ion etch step is carried out using chlorine chemistry.

7. A method of fabricating a transistor according to claim 5 further comprising the step of metallizing each via to provide a conductive path through the silicon carbide substrate to each respective source, gate, and drain contact.