METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE

• US 20110167238A1
• Filed: 03/14/2011
• Published: 07/07/2011
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Granted Patent: US 8,086,815 B2
• Time in Patent Office: Days
• US Class Current: 711/168
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Claims

1. A processor-based system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a memory hub controller storing a plurality of memory requests and outputting each stored memory request responsive to a flow control signal generated as a function of received memory request status signals, the memory hub controller further receiving and storing read data and the memory request status signals, the memory hub controller outputting the stored read data; and

a plurality of memory modules coupled to the memory hub controller, wherein the memory modules further comprise;

a memory hub having a response generator, the response generator having a first input terminal operable to receive read data signals from the memory controller, a second input terminal operable to receive read status signals, the read status signals identifying read requests corresponding to each read data signal, and an output terminal, the response generator operable to generate read responses each comprising one of the read data signals and corresponding read status signals, the response generator further being operable to transmit the read responses from the output terminal to the memory hub controller.