NANOWIRE AND LARGER GaN BASED HEMTS

• US 20110169012A1
• Filed: 10/06/2008
• Published: 07/14/2011
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Wang, Xin, Hersee, Stephen D.
• Granted Patent: US 8,188,513 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body

Abstract

Nanowire and larger, post-based HEMTs, arrays of such HEMTs, and methods for their manufacture are provided. In one embodiment, a HEMT can include a III-N based core-shell structure including a core member (e.g., GaN), a shell member (e.g., AlGaN) surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at the interface therebetween. The core member including a nanowire and/or a post can be disposed over a doped buffer layer and a gate material can be disposed around a portion of the shell member. Exemplary methods for making the nanowire HEMTs and arrays of nanowire HEMTs can include epitaxially forming nanowire(s) and epitaxially forming a shell member from each formed nanowire. Exemplary methods for making the post HEMTs and arrays of post HEMTs can include etching a III-N layer to form II-N post(s) followed by formation of the shell member(s).

Claims

1. A high electron mobility transistor (HEMT) comprising:

a III-N based core-shell structure comprising a core member, a shell member surrounding a length of the core member and a two-dimensional electron gas (2-DEG) at an interface between the core member and the shell member;

a doped buffer layer having the core member disposed over a first portion of the doped buffer layer; and

a gate material disposed around a portion of the shell member and over a second portion of the doped buffer layer.

2. The HEMT of claim 1, further comprising,

a first dielectric layer disposed around a first portion of the shell member and over the doped buffer layer;

a gate metal disposed around a second portion of the shell member and over a portion of the first dielectric layer; and

a second dielectric layer disposed around a third portion of the shell member and over a portion of the gate metal.

3. The HEMT of claim 1, further comprising,

a source contact disposed on the III-N based core sell structure;

and

a drain contact with the doped buffer layer disposed thereon.

4. The HEMT of claim 1, wherein the core member comprises a nanowire or a larger post.

5. The HEMT of claim 1, wherein the core member comprises a cross-sectional shape selected from the group consisting of a polygon, a rectangle, a square, an oval, and a circle.

6. The HEMT of claim 1, wherein the core member has a hexagonal cross-sectional shape.

7. The HEMT of claim 1, wherein the core member comprises a nanowire having an aspect ratio of about 100 or higher and a cross-sectional dimension of about 250 nm or less.

8. The HEMT of claim 1, wherein the core member comprises a larger post having a minor cross-sectional dimension of greater than about 250 nm.

9. The HEMT of claim 1, wherein each of the core member, the shell member, and the doped buffer layer comprises one or more materials comprising GaN, AlN, InN, InGaN, AlInGaN or AlGaN.

10. The HEMT of claim 1, wherein the core member comprises GaN and the shell member comprises AlGaN having a doped AlGaN region and an undoped AlGaN region.

11. The HEMT of claim 1, wherein the shell member comprises a multilayer structure comprising a plurality of III-N alloys comprising GaN, AlN, InN, InGaN, AlInGaN or AlGaN.

12. The HEMT of claim 1, wherein the shell member has a thickness of about 0.1 μ

m to about 0.3 μ

m.

13. The HEMT of claim 1, further comprising a selective growth mask disposed over the doped buffer layer, wherein a nanowire core member extends from the doped buffer layer through the selective growth mask.

14. The HEMT of claim 1, wherein the gate material has a short length of about 1 micron or less.

15. A HEMT transistor array comprising a plurality of HEMTs of claim 1.

16. A device comprising one or more HEMT transistor arrays of claim 15, wherein the device comprises a cell phone, a direct broadcast satellite receiver, or a radar.

17. A method for making a HEMT comprising:

epitaxially growing a III-N based nanowire through a growth mask from a first portion of a doped buffer layer;

forming a shell member surrounding a length of the III-N based nanowire for forming a two-dimensional electron gas (2-DEG) at an interface between the III-N based nanowire and the shell member, the shell member being disposed over a second portion of the doped buffer layer;

forming a first dielectric layer surrounding a first portion of the shell member and over a third portion of the doped buffer layer;

forming a metal gate surrounding a second portion of the shell member and over the first dielectric layer; and

forming a second dielectric layer surrounding a third portion of the shell member and over a portion of the metal gate.

18. The method of claim 17, further comprising,

forming a source contact on the III-N based nanowire;

and

forming a drain contact on the doped buffer layer opposite to the III-N based nanowire.

19. The method of claim 17, wherein epitaxially growing the III-N based nanowire comprises a selective growth of the III-N based nanowire followed by a pulsed growth of the III-N based nanowire.

20. The method of claim 19, wherein forming the shell member surrounding the length of the III-N based nanowire comprises adding trimethyl aluminum to an MOCVD (metalorganic chemical vapour deposition) gas mixture containing trimethylgallium (TMGa), and ammonia (NH₃) during the pulsed growth.

21. A method for making a HEMT transistor array according to claim 17, further comprising:

epitaxially growing a plurality of III-N based nanowires through the growth mask from the doped buffer layer;

forming a shell member surrounding a length of each nanowire of the plurality of III-N based nanowires for forming a two-dimensional electron gas (2-DEG) at an interface between each III-N based nanowire and the shell member,

forming the first dielectric layer surrounding a first portion of each shell member and over the doped buffer layer;

forming the metal gate surrounding a second portion of each shell member and over the first dielectric layer; and

forming the second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

22. A method for making a HEMT comprising:

forming a III-N based post over a first portion of a doped buffer layer, wherein the III-N based post has a minor cross-sectional dimension of greater than about 250 nm;

forming a shell member surrounding a length of the III-N based post for forming a two-dimensional electron gas (2-DEG) at an interface between the III-N based post and the shell member, the shell member being disposed over a second portion of the doped buffer layer;

forming a first dielectric layer surrounding a first portion of the shell member and over a third portion of the doped buffer layer;

forming a metal gate surrounding a second portion of the shell member and over the first dielectric layer; and

forming a second dielectric layer surrounding a third portion of the shell member and over a portion of the metal gate.

23. The method of claim 22, further comprising, forming a source contact on the III-N based post;

and

forming a drain contact having the doped buffer layer disposed there on.

24. The method of claim 22, wherein forming the III-N based post over the first portion of the doped buffer layer comprises,

forming a III-N based layer over the doped buffer layer;

and

top-down etching the III-N based layer to form the III-N based post having a length and a cross-sectional shape.

25. A method for making a HEMT transistor array according to claim 22, further comprising:

forming a plurality of III-N based posts over the doped buffer layer;

wherein each post of the plurality of III-N based posts has a minor cross-sectional dimension of greater than about 250;

forming a shell member surrounding a length of each post of the plurality of III-N based posts for forming a two-dimensional electron gas (2-DEG) at an interface between each III-N based nanowire and the shell member,

forming the first dielectric layer surrounding a first portion of each shell member over the doped buffer layer;

forming a metal gate surrounding a second portion of each shell member and over the first dielectric layer; and

forming a second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.