HYDROGEN ION-SENSITIVE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

• US 20110169056A1
• Filed: 03/16/2010
• Published: 07/14/2011
• Est. Priority Date: 01/11/2010
• Status: Active Grant

• Current Assignee: National Applied Research Laboratories (Government of The Republic of China)
• Original Assignee: National Chip Implementation Center National Applied Research Laboratories
• Inventors: Lin, Chen-Fu, Chiu, Chin-Fong, Tsai, Hann-Huei, Juang, Ying-Zong, Wey, Chin-Long
• Granted Patent: US 8,466,521 B2
• Time in Patent Office: Days
• US Class Current: 257/253
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

Claims

1. A hydrogen ion-sensitive field effect transistor (FET), comprising:

a semiconductor substrate which has a gate area defined thereon and further has a source area and a drain area;

an insulating layer formed within the gate area on the semiconductor substrate;

a transistor gate deposited within the gate area and having a first gate layer, wherein the first gate layer is an aluminum layer and has a sensing window defined thereon; and

a sensing film formed within the sensing window, wherein the sensing film is an alumina layer formed by oxidizing the first gate layer.

2. The hydrogen ion-sensitive FET of claim 1, wherein the first gate layer makes contact with the insulating layer.

3. The hydrogen ion-sensitive FET of claim 1, wherein the transistor gate further comprises a second gate layer, and the second gate layer makes contact with the insulating layer.

4. The hydrogen ion-sensitive FET of claim 1, further comprising a passivation layer formed with a first opening corresponding in position to the sensing window so as to expose the first gate layer.

5. The hydrogen ion-sensitive FET of claim 4, further comprising a conductor and a reference electrode layer, wherein the conductor and the transistor gate are formed in a same manufacturing process, and the reference electrode layer is provided on the conductor and exposed through the passivation layer.

6. A method for manufacturing a hydrogen ion-sensitive field effect transistor (FET), comprising steps of:

providing a semiconductor substrate having a source area, a drain area, and an insulating layer formed thereon, wherein the insulating layer is provided within a gate area on the semiconductor substrate;

performing a gate manufacturing process in which an aluminum layer is deposited within the gate area to form a first gate layer;

defining a sensing window on the first gate layer; and

forming a sensing film by exposing the sensing window of the first gate layer to an oxygen-containing gas, thus forming an alumina layer for use as the sensing film.

7. The method of claim 6, wherein the first gate layer makes contact with the insulating layer.

8. The method of claim 6, wherein the step of performing the gate manufacturing process further comprises:

forming a second gate layer within the gate area, wherein the second gate layer makes contact with the insulating layer.

9. The method of claim 6, further comprising, subsequent to the gate manufacturing process:

forming a passivation layer having a first opening corresponding in position to the sensing window so as to expose the first gate layer.

10. The method of claim 9, further comprising:

forming a conductor during the gate manufacturing process;

forming a second opening to expose the conductor through the passivation layer; and

forming a reference electrode layer which is provided on the conductor, corresponds in position to the second opening, and is exposed through the passivation layer.