3D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20110169072A1
• Filed: 12/21/2010
• Published: 07/14/2011
• Est. Priority Date: 01/11/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LIM, Se-Yun, Choi, Eun-Seok
• Granted Patent: US 8,482,051 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A 3D nonvolatile memory device includes a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked, a plurality of channel contacts coupled to the plurality of channel layers, respectively, and a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

Claims

1. A 3D nonvolatile memory device comprising:

a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked;

a plurality of channel contacts coupled to the plurality of channel layers, respectively; and

a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

2. The 3D nonvolatile memory device of claim 1, further comprising a plurality of selection transistors buried in the plurality of selection lines and coupled to the channel contacts.

3. The 3D nonvolatile memory device of claim 2, wherein the selection transistor has a gate all around (GAA) structure.

4. The 3D nonvolatile memory device of claim 2, wherein each of the selection transistors comprises a pillar-type channel coupled to a corresponding channel contact among the plurality of channel contacts.

5. The 3D nonvolatile memory device of claim 2, wherein each of the selection transistors comprises:

a pillar-type channel coupled to a corresponding channel contact among the plurality of channel contacts;

a gate dielectric layer surrounding the pillar-type channel; and

a gate electrode surrounding the gate dielectric layer.

6. The 3D nonvolatile memory device of claim 2, further comprising a bit line formed over the selection lines, coupled to the channel contacts through the selection transistors, and crossing over the selection lines.

7. The 3D nonvolatile memory device of claim 6, wherein the bit line extends in the same direction as the channel structure.

8. The 3D nonvolatile memory device of claim 1, wherein each of the selection lines is a drain selection line.

9. The 3D nonvolatile memory device of claim 1, wherein the selection lines are formed as a single layer and coupled to the plurality of channel contacts, respectively.

10. The 3D nonvolatile memory device of claim 1, wherein the selection lines are formed as a plurality of layers.

11. The 3D nonvolatile memory device of claim 10, wherein the selection lines comprise:

a plurality of first selection lines coupled to one or more channel contacts, respectively; and

a plurality of second selection lines formed over the first selection lines and coupled to the other channel contacts, respectively, wherein the first selection lines and the second selection lines does not overlap each other.

12. The 3D nonvolatile memory device of claim 10, wherein the selection lines comprise:

a plurality of first selection lines each coupled to at least two adjacent channel contacts; and

a plurality of second selection lines formed over the first selection lines and each coupled to at least two adjacent channel contacts, wherein the channel contacts of first selection lines are partially shared with that of the second selection lines.

13. The 3D nonvolatile memory device of claim 1, wherein the channel structure is patterned in a stepped shape to expose the plurality of channel layers.

14. The 3D nonvolatile memory device of claim 1, wherein the plurality of channel layers and interlayer dielectric layers are alternately stacked along an etched surface of a trench formed by etching a substrate to form the plurality of channel structures.

15. The 3D nonvolatile memory device of claim 1, wherein, the channel layers of the adjacent channel structures are isolated from each other, and the channel layers formed at the lowermost layer are isolated by the interlayer dielectric layer.

16. A method for fabricating a 3D nonvolatile memory device, comprising:

forming a plurality of channel structures each comprising a plurality of channel layers and interlayer dielectric layers which are alternately stacked;

forming a plurality of channel contacts coupled to the plurality of channel layers, respectively; and

forming a plurality of selection lines vertically-coupled to the plurality of channel contacts and crossing over the plurality of channel structures.

17. The method of claim 16, further comprising forming a plurality of selection transistors buried in the plurality of selection lines, coupled to the channel contacts, and having a gate all around (GAA) structure, after the forming of the plurality of selection lines.

18. The method of claim 16, wherein the forming of the plurality of channel structures comprises:

forming the plurality of channel layers and interlayer dielectric layers alternately over a substrate; and

forming the plurality of channel structures by etching the plurality of channel layers and interlayer dielectric layers, such that the channel layers included in the adjacent channel structures are isolated from each other.

19. The method of claim 18, wherein the forming of the plurality of channel structures comprises patterning the etched channel layers and interlayer dielectric layers in a stepped shape to expose the plurality of channel layers.

20. The method of claim 16, wherein the forming of the plurality of channel structures comprises:

forming a trench by etching a substrate; and

stacking the plurality of channel layers and interlayer dielectric layers alternately along an etched surface of the trench.

21. The method of claim 16, wherein the forming of the plurality of channel structures comprises:

forming a block isolation insulation layer over a substrate;

forming a trench by etching the block isolation insulation layer; and

stacking the plurality of channel layers and interlayer dielectric layers alternately along an etched surface of the trench.

22. The method of claim 16, wherein the forming of the plurality of selection lines comprises:

forming a first interlayer dielectric layer over the resultant structure having the channel contacts formed therein;

forming a plurality of conductive layers for the selection lines over the first interlayer dielectric layer; and

forming a second interlayer dielectric over the resultant structure having the plurality of conductive layers formed thereon.

23. The method of claim 22, further comprising, after the forming of the second interlayer dielectric layer:

forming a plurality of trenches exposing the surfaces of the channel contacts, respectively, by etching the second interlayer dielectric layer, the conductive layers, and the first interlayer dielectric layer;

forming a gate dielectric layer on inner walls of the trenches; and

forming a plurality of selection transistors having a gate all around (GAA) structure by filling a channel layer in the plurality of trenches having the gate dielectric layer formed therein.

24. The method of claim 23, further comprising forming a bit line over the third interlayer dielectric layer, the bit line coupled to the selection transistors and extending in the same direction as the channel structure, after the forming of the plurality of selection transistors.

25. The method of claim 16, wherein the forming of the plurality of channel contacts comprises:

forming a first interlayer dielectric layer over the resultant structure having the plurality of channel structures formed therein;

forming a plurality of contact holes by selectively etching the first interlayer dielectric layer, the contact holes exposing the plurality of channel layers, respectively; and

forming the plurality of channel contacts by filling a conductive layer in the plurality of contact holes.

26. The method of claim 25, wherein the forming of the plurality of selection lines comprises:

exposing upper portions of the channel contacts by etching the first interlayer dielectric layer between the plurality of channel contacts to a predetermined depth;

forming a gate dielectric layer over the exposed channel contacts and the first interlayer dielectric layer;

forming a conductive layer for the selection line over the resultant structure having the gate dielectric layer formed thereon; and

forming the plurality of selection lines and a plurality of selection transistors buried in the selection lines and having a gate all around (GAA) structure by patterning the conductive layer.

27. The method of claim 26, further comprising, after the forming of the plurality of selection lines and the plurality of selection transistors:

forming a second interlayer dielectric layer over the entire surface of the resultant structure having the selection lines and the selection transistors formed therein;

forming a plurality of trenches exposing the channel contacts by etching the second interlayer dielectric layer and the gate dielectric layer;

forming a plurality of contacts by filling a conductive layer in the plurality of trenches; and

forming a bit line over the second interlayer dielectric layer, the bit line coupled to the selection transistors through the contacts and extending in the same direction as the channel structure.

28. The method of claim 26, further comprising, after the forming of the plurality of selection lines and the plurality of selection transistors:

forming a second interlayer dielectric layer over the entire surface of the resultant structure having the selection lines and the selection transistors formed therein;

performing a planarization process on the resultant structure having the second interlayer dielectric layer formed thereon, until the channel contacts are exposed; and

forming a bit line coupled to the selection transistors through the channel contacts and extending in the same direction as the channel structure.

29. The method of claim 16, wherein the forming of the plurality of selection lines comprises:

forming a first interlayer dielectric layer over the resultant structure having the channel contacts formed therein;

forming a first conductive layer for a primary selection line over the first interlayer dielectric layer such that the first conductive layer is positioned over on or more channel contacts among the plurality of channel contacts;

forming a second interlayer dielectric layer over the resultant structure having the first conductive layer formed thereon;

forming a second conductive layer for a secondary selection line over the resultant structure having the second interlayer dielectric layer formed thereon such that the second conductive layer is positioned over the other channel contacts among the plurality of channel contacts; and

forming a third interlayer dielectric layer over the resultant structure having the second conductive layer formed thereon.

30. The method of claim 29, further comprising, after the forming of the third interlayer dielectric layer:

forming a plurality of trenches exposing the surfaces of the channel contacts, respectively, by etching the third interlayer dielectric layer, the second interlayer dielectric layer, the first conductive layer, and the first interlayer dielectric layer or etching the third interlayer dielectric layer, the second conductive layer, the second interlayer dielectric layer, and the first interlayer dielectric layer;

forming a gate dielectric layer on inner walls of the trenches; and

forming a plurality of selection transistors having a gate all around (GAA) structure by filling a channel layer in the plurality of trenches having the gate dielectric layer formed therein.

31. The method of claim 30, after the forming of the plurality of selection transistors, further comprising forming a bit line over the third interlayer dielectric layer, the bit line coupled to the selection transistors and extending in the same direction as the channel structure.

32. The method of claim 16, wherein the forming of the plurality of selection lines comprises:

forming a first interlayer dielectric layer over the resultant structure having the channel contacts formed therein;

forming a first conductive layer for a first selection line over the first interlayer dielectric layer such that the first conductive layer covers at least two adjacent channel contacts;

forming a second interlayer dielectric layer over the resultant structure having the first conductive layer formed thereon;

forming a second conductive layer for a second selection line over the resultant structure having the second interlayer dielectric layer formed thereon such that the second conductive layer covers at least two adjacent channel contacts and overlaps the first conductive layer to share some channel contacts; and

forming a third interlayer dielectric layer over the resultant structure having the second conductive layer formed thereon.

33. The method of claim 32, further comprising, after the forming of the third interlayer dielectric layer:

forming a plurality of trenches exposing the surfaces of the channel contacts, respectively, by etching the third interlayer dielectric layer, the second conductive layer, the second interlayer dielectric layer, the first conductive layer, and the first interlayer dielectric layer;

forming a gate dielectric layer on inner walls of the trenches; and

forming a plurality of selection transistors having a gate all around (GAA) structure by filling a channel layer in the plurality of trenches having the gate dielectric layer formed therein.

34. The method of claim 33, after the forming of the plurality of selection transistors, further comprising forming a bit line over the third interlayer dielectric layer, the bit line coupled to the selection transistors and extending in the same direction as the channel structure.

35. A method for fabricating a 3D nonvolatile memory device, comprising:

forming a channel structure comprising a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and a first interlayer dielectric layer covering the channel structure;

forming a plurality of channel contacts passing through the first interlayer dielectric layer and coupled to the plurality of channel layers, respectively; and

forming a plurality of selection lines covering the channel contacts and including a low-resistance material and a plurality of selection transistors buried in the selection lines and coupled to the channel contacts.

36. The method of claim 35, wherein the forming of the plurality of selection lines and the plurality of selection transistors comprises:

forming the selection lines crossing over the channel structure at an area of the channel contacts and including a metallic layer; and

forming the selection transistors buried in the selection lines and coupled to the channel contacts, the selection transistors having a gate all around (GAA) structure.

37. The method of claim 36, wherein the metallic layer comprises any one selected from the group consisting of a metal layer, a metal oxide layer, a metal nitride layer, and a metal silicide layer.

38. The method of claim 35, further comprising:

forming a second interlayer dielectric layer over the first interlayer dielectric layer, before the selection lines are formed;

forming a third interlayer dielectric layer over the second interlayer dielectric layer, after the selection lines are formed; and

forming a bit line over the third interlayer dielectric layer, after the selection transistors are formed, the bit line coupled to the selection transistors and crossing over the selection lines.

39. The method of claim 38, wherein the forming of the selection lines comprises:

forming a conductive layer for the selection line over the second interlayer dielectric layer; and

etching the conductive layer such that the conductive layer covers upper portions of the channel contacts.

40. The method of claim 38, wherein the forming of the selection transistors comprises:

forming a hole by etching the third interlayer dielectric layer and the selection line;

forming a gate electrode on inner walls of the hole, the gate electrode including a silicon layer;

extending the hole by etching the second interlayer dielectric layer at the bottom of the hole to expose the channel contact; and

forming a gate dielectric layer on inner walls of the extended hole; and

forming a pillar-type channel which fills the extended hole.

41. The method of claim 40, wherein the selection line is formed to surround an outer wall of the hole.

42. The method of claim 35, wherein the forming of the plurality of selection lines and the plurality of selection transistors comprises:

forming the selection transistors over the first interlayer dielectric layer, the selection transistors coupled to the channel contacts and having a gate all around (GAA) structure; and

forming the selection lines over the first interlayer dielectric layer, wherein the selection lines are coupled to the adjacent selection transistors and include a metallic layer.

43. The method of claim 42, wherein the metallic layer comprises any one selected from the group consisting of a metal layer, a metal oxide layer, a metal nitride layer, and a metal silicide layer.

44. The method of claim 42, further comprising forming a bit line over the selection lines, the bit line crossing over the selection lines and coupled to the channel contacts through the selection transistors.

45. The method of claim 42, wherein the forming of the selection transistors comprises:

recessing the first interlayer dielectric layer to a predetermined depth such that the channel contacts partially protrude from the recessed first interlayer dielectric layer;

forming a gate dielectric layer to surround the protruding channel contacts; and

forming a gate electrode to surround the protruding channel contacts with the gate dielectric layer therebetween, the gate electrode including a silicon layer.

46. The method of claim 42, wherein the forming of the selection lines comprises:

forming a conductive layer over the first interlayer dielectric layer;

slimming the conductive layer such that the upper surface of the conductive layer is set to a lower level than the upper surface of the gate electrode; and

patterning the conductive layer to surround the gate electrode and couple the adjacent gate electrodes.

47. The method of claim 35, wherein each of the selection lines is a drain selection line.