STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS

• US 20110169127A1
• Filed: 03/21/2011
• Published: 07/14/2011
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: HSU, Louis L., Yang, Chih-Chao, Tonti, William R.
• Granted Patent: US 8,232,649 B2
• Time in Patent Office: Days
• US Class Current: 257/529
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Claims

1. A structure comprising:

a wiring interconnect structure having an interface comprising a metal wiring layer and a capping layer of a first material type; and

an electronic fuse interconnect structure having an interface comprising a metal wiring layer and a capping layer of a second material type.

2. The structure of claim 1, wherein the interface of the electronic fuse interconnect structure includes a metal layer and the capping layer which comprises SiN and the interface of the wiring interconnect structure includes a metal layer and the capping layer comprises one of:

Co(W,P,B), Ru, Ir, Rh and Pt.

3. The structure of claim 1, wherein the first material type is different than the second material type.

4. The structure of claim 1, wherein the second material type and/or the metal wiring layer of the electron fuse interconnect structure is damaged thereby exhibiting degraded interfacial properties between the metal wiring layer and the second material type.

5. The structure of claim 4, wherein the damage is a treatment from one of radiation sources and laser light.

6. The structure of claim 1, wherein the wiring interconnect structure has a greater electromigration (EM) resistance than the electronic fuse interconnect structure and the second material type in combination with a metal layer is configured to provide EM resistance.

7. The structure of claim 1, further comprising a third interconnect structure having a third interfacial structure, different from a first and second interfacial structure of the electronic fuse interconnect structure and the wiring interconnect structure.

8. A structure comprising:

a first macro having a metal wiring layer on a first level electrically connected to a metal wiring layer on a second layer and a capping layer over the metal wiring layer on the second layer which has a first electromigration (EM) resistance; and

a second macro adjacent the first macro, the second macro having a metal wiring layer on the first level electrically connected to a metal wiring layer on the second layer and a capping layer over the metal wiring layer on the second layer which has a second electromigration (EM) resistance different from the first electromigration (EM) resistance.

9. The structure of claim 8, wherein the capping layer of the first macro is SiN and the capping layer of the second macro is one of Co(W,P,B), Ru, Ir, Rh and Pt.

10. The structure of claim 8, wherein the capping layer of the first and the second macro is a same material, and the capping layer on the second macro and/or the metal wiring layer on the second layer of the second macro is damaged thereby providing a degraded electromigration (EM) resistance than that of the first macro.

11. An interconnect structure comprising:

a first macro having a first e-fuse programmability comprising an upper wiring layer capped by a capping material; and

a second macro having a second e-fuse programmability comprising an upper wiring layer capped by a capping material having interfacial properties which are different than that of the first macro.

12. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a first macro having a first interfacial structure; and

a second macro having a second interfacial structure, different from the first interfacial structure.

13. The design structure of claim 12, wherein the design structure comprises a netlist.

14. The design structure of claim 12, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

15. The design structure of claim 12, wherein the design structure resides in a programmable gate array.