CHIP PACKAGE AND FABRICATION METHOD THEREOF

• US 20110169159A1
• Filed: 06/15/2010
• Published: 07/14/2011
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: LIN, Chia-Sheng, Lee, Po-Han
• Granted Patent: US 8,952,519 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3178 : Coating or filling in grooves made in the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Abstract

A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Claims

1. A chip package, comprising:

a semiconductor substrate, having a first surface and an opposing second surface;

a spacer disposed under the second surface of the semiconductor substrate;

a cover plate disposed under the spacer;

a recessed portion adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer; and

a protection layer disposed over the first surface of the semiconductor substrate and in the recessed portion.

2. The chip package as claimed in claim 1, wherein the recessed portion further extends to the cover plate.

3. The chip package as claimed in claim 2, wherein the recessed portion has an inclined plane.

4. The chip package as claimed in claim 3, wherein the protection layer covers the inclined plane of the recessed portion.

5. The chip package as claimed in claim 1, further comprising:

a through hole disposed on the first surface of the semiconductor substrate, extending from the first surface to the second surface of the semiconductor substrate;

a conductive trace layer conformally disposed over the first surface and in the through hole; and

a buffer plug disposed in the through hole over the conductive trace layer, wherein the protection layer covers the buffer plug in the through hole.

6. The chip device package as claimed in claim 5, wherein the buffer plug is not completely cured and softer than the protection layer in the through hole.

7. The chip package as claimed in claim 5, further comprising an insulating layer disposed between the semiconductor substrate and the conductive trace layer, wherein the buffer plug has a coefficient of thermal expansion between a coefficient of thermal expansion of the protection layer and a coefficient of thermal expansion of the insulating layer.

8. The chip device package as claimed in claim 5, wherein the buffer plug comprises one or more than one layers of photosensitive material.

9. The chip device package as claimed in claim 5, wherein the buffer plugs disposed in at least two through holes have different shapes at a cross section.

10. A method for fabricating a chip package, comprising:

providing a semiconductor substrate, having a first surface and an opposing second surface;

forming a spacer under the second surface of the semiconductor substrate;

providing a cover plate to attach under the spacer;

forming trench openings on the first surface of the semiconductor substrate along a scribe line, extending from the first surface to at least the spacer;

forming a protection layer over the first surface of the semiconductor substrate and in the trench openings; and

dicing the semiconductor substrate along the scribe line to form chip packages, wherein each chip package includes at least a recessed portion adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer, and covered with the protection layer.

11. The method as claimed in claim 10, wherein the trench openings are formed by a pre-cutting process.

12. The method as claimed in claim 10, wherein the trench openings further extend to the cover plate.

13. The method as claimed in claim 12, wherein the recessed portion has an inclined plane and the inclined plane is covered with the protection layer.

14. The method as claimed in claim 10, further comprising:

forming through holes on the first surface of the semiconductor substrate, extending from the first surface to the second surface of the semiconductor substrate;

forming a conductive trace layer on the first surface of the semiconductor substrate and in the through holes; and

forming a buffer plug over the conductive trace layer in each through hole, wherein the protection layer covers the buffer plugs in the through holes.

15. The method as claimed in claim 14, wherein the through holes are formed before the step of forming the trench openings.

16. The method as claimed in claim 14, wherein the step of forming the buffer plug comprises:

coating a buffer material, covering the first surface of the semiconductor substrate and filling the through holes;

patterning the buffer material by an exposure process and a development process so that the buffer material remains in the through holes; and

curing the buffer material not completely to form the buffer plugs, wherein the buffer plugs in at least two of the through holes have different shapes at a cross section.

17. The method as claimed in claim 14, further comprising:

forming an insulating material, conformally covering the first surface of the semiconductor substrate and extending to sidewalls and bottom sides of the through holes; and

patterning the insulating material, to remove the portions of the insulating material on the bottom sides of the through holes to form an insulating layer.

18. The method as claimed in claim 17, wherein the buffer plug has a coefficient of thermal expansion between a coefficient of thermal expansion of the protection layer and a coefficient of thermal expansion of the insulating layer.

19. The method as claimed in claim 14, wherein the buffer plug comprises one or more than one layers of photosensitive material.

20. The method as claimed in claim 14, wherein the buffer plug is softer than the protection layer.