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Dual Interconnection in Stacked Memory and Controller Module

  • US 20110169171A1
  • Filed: 03/18/2011
  • Published: 07/14/2011
  • Est. Priority Date: 04/28/2009
  • Status: Abandoned Application
First Claim
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1. Apparatus comprising:

  • an integrated circuit die having a topside and a bottom side;

    an integrated circuit formed in the topside of said die;

    a plurality of topside contact terminals;

    said integrated circuit having two groups of signals, a first group consisting of slow speed signals and a second group consisting of high-speed signals;

    the integrated circuit having means for connecting the slow speed signals to a first group of topside contact terminals;

    the integrated circuit having means for connecting the high speed signals to a second group of topside contact terminals;

    a plurality of edge electrical connectors connected to said first group of topside contact terminals;

    a plurality of through-hole vias connected to said second group of topside contact terminals; and

    a plurality of via electrical connectors connected to said second group of topside contact terminals through said through-hole vias;

    whereby the high-speed signals are connected to the via electrical connectors and the slow speed signals are connected to the edge electrical connectors.

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