INSPECTION GUIDED OVERLAY METROLOGY

• US 20110170091A1
• Filed: 01/05/2011
• Published: 07/14/2011
• Est. Priority Date: 01/11/2010
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Widmann, Amir, Park, Allen, Chang, Ellis
• Granted Patent: US 8,559,001 B2
• Time in Patent Office: Days
• US Class Current: 356/237.5
• CPC Class Codes: G01N 2021/8822 Dark field detection
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Claims

1. A method for inspection guided overlay metrology, comprising:

performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer;

generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer;

identifying one or more defects within each of the one or more generated care areas by performing an inspection scan of each of the one or more generated care areas, wherein the inspection scan includes a low-threshold inspection scan or a high sensitivity inspection scan;

identifying one or more overlay sites of at least some of the one or more instances of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique;

comparing location data of the one or more identified defects of a generated care area to location data of the one or more identified overlay sites within the generated care area in order to identify one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites; and

generating a metrology sampling plan based on the identified one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites.

2. The method of claim 1, wherein the defect inspection technique comprises:

a virtual inspection technique.

3. The method of claim 1, wherein the defect inspection technique includes one of the group including a bright-field inspection technique, a dark-field inspection technique, and an electron beam inspection technique.

4. The method of claim 1, wherein the predetermined pattern of the semiconductor wafer is formed at multiple locations on the semiconductor wafer.

5. The method of claim 1, wherein the predetermined pattern of the semiconductor wafer is a pattern of interest (POI).

6. The method of claim 1, further comprising:

selecting a predetermined pattern for an overlay metrology measurement of a semiconductor wafer.

7. The method of claim 1, wherein the generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer comprises:

generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer utilizing a context based inspection process.

8. The method of claim 6, wherein the generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer utilizing a context based inspection process comprises:

selecting a region of interest in a full die image;

extracting a design from the selected region of interest;

extracting one or more hot spots for the extracted design; and

generating a care area for the extracted hot spots.

9. The method of claim 1, wherein the generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer comprises:

generating a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer based on one or more results of a cell names search process.

10. The method of claim 1, wherein the performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer comprises:

performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer utilizing design data of the semiconductor wafer.

11. The method of claim 1, wherein the performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer comprises:

performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer utilizing a design based binning technique.

12. The method of claim 11, wherein the performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer utilizing a design based binning technique comprises:

performing a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer by binning defects detected on the wafer in groups such that portions of design data proximate positions of the defects in each of the groups are at least similar.

13. The method of claim 1, wherein the identifying one or more defects within each of the one or more generated care areas by performing an inspection scan of each of the one or more generated care areas, wherein the inspection scan includes a low-threshold inspection scan or a high sensitivity inspection scan, comprises:

identifying one or more defects within each of the one or more generated care areas by performing an inspection scan of each of the one or more generated care areas, wherein the inspection scan is performed on each of the one or more generated care areas utilizing an inspection recipe optimized for each of the one or more generated care areas.

14. The method of claim 1, wherein the generated metrology sampling plan is suitable for critical dimension metrology.

15. The method of claim 1, wherein generating a metrology sampling plan based on the identified one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites comprises:

dynamically generating a metrology sampling plan based on the identified one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites.

16. The method of claim 1, further comprising:

measuring overlay error at the identified one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites utilizing the generated metrology sampling plan.

17. A system for inspection guided overlay metrology, comprising:

an inspection system configured to detect defects on a semiconductor wafer;

a metrology system configured to measure overlay error at one or more locations of a selected pattern on a semiconductor wafer; and

a computer system configured to;

perform a pattern search in order to identify one or more instances of a predetermined pattern on a semiconductor wafer;

generate a care area for each of the one or more instances of the predetermined pattern on the semiconductor wafer;

identify one or more defects within each of the one or more generated care areas by performing an inspection scan of each of the one or more generated care areas, wherein the inspection scan includes a low-threshold inspection scan or a high sensitivity inspection scan;

identify one or more overlay sites of at least some of the one or more instances of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique;

compare location data of the one or more identified defects of a generated care area to location data of the one or more identified overlay sites within the generated care area in order to identify one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites; and

generate a metrology sampling plan based on the identified one or more locations wherein the one or more defects are proximate to the one or more identified overlay sites.

18. The method of claim 17, wherein the inspection system includes one of the group including a bright-field inspection system, a dark-field inspection system, and an electron beam inspection system.

19. The method of claim 17, wherein the metrology system is configured to perform critical dimension metrology.

20. The method of claim 17, wherein the metrology system is configured to utilize the generated metrology sampling plan.

21. The method of claim 17, wherein the metrology system and the inspection system are configured to operate utilizing a common coordinate system.

22. The method of claim 17, wherein the computer system is configured to utilize design data of the semiconductor wafer in order to correlate location data of the one or more identified defects of a generated care area to location data of the one or more identified overlay sites within the generated care area.