CHIP PACKAGE AND FABRICATION METHOD THEREOF

• US 20110170303A1
• Filed: 01/13/2011
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Abandoned Application

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: Liu, Tsang-Yu, Wu, Shang-Yi
• Application Number:
  US13/005,692
• Publication Number:
  US 20110170303A1
• Time in Patent Office: Days
• US Class Current: 362/382
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

A chip package includes a substrate having an upper, a lower, a first side, and a second side surfaces, a chip having a first and a second electrodes, a first trench extending from the upper surface toward the lower surface and from the first side surface toward an inner portion of the substrate, a first conducting layer overlying a sidewall of the first trench and electrically connecting the first electrode, which is not coplanar with the first side surface and separated from the first side surface by a first distance, a second trench extending from the upper surface toward the lower surface and from the second side surface toward the inner portion, and a second conducting layer overlying a sidewall of the second trench and electrically connecting the second electrode, which is not coplanar with the second side surface and separated from the second side surface by a second distance.

Claims

1. A chip package, comprising:

a carrier substrate having an upper surface and an opposite lower surface and having a first side surface and a second side surface;

a chip disposed on the upper surface or the lower surface of the carrier substrate and having a first electrode and a second electrode;

a first trench extending from the upper surface toward the lower surface of the carrier substrate and extending from the first side surface toward an inner portion of the carrier substrate;

a first conducting layer located on a sidewall of the first trench and electrically connected to the first electrode, wherein the first conducting layer is not coplanar with the first side surface and is separated from the first side surface by a first minimum distance;

a second trench extending from the upper surface toward the lower surface of the carrier substrate and extending from the second side surface toward the inner portion of the carrier substrate; and

a second conducting layer located on a sidewall of the second trench and electrically connected to the second electrode, wherein the second conducting layer is not coplanar with the second side surface and is separated from the second side surface by a second minimum distance.

2. The chip package as claimed in claim 1, wherein the first side surface is opposite to the second side surface.

3. The chip package as claimed in claim 1, wherein the first side surface is substantially perpendicular to the second side surface.

4. The chip package as claimed in claim 1, wherein the first side surface and the second side surface are a same side surface.

5. The chip package as claimed in claim 1, further comprising an insulating layer located between the first conducting layer and the carrier substrate.

6. The chip package as claimed in claim 1, further comprising an insulating layer located between the second conducting layer and the carrier substrate.

7. The chip package as claimed in claim 1, further comprising a recess extending from the upper surface toward the lower surface, wherein the chip is disposed on a bottom portion of the recess.

8. The chip package as claimed in claim 1, wherein the chip is a light emitting chip.

9. The chip package as claimed in claim 8, further comprising a circuit board having a first pad and a second pad located on a surface of the circuit board, wherein the carrier substrate is disposed on the circuit board and the first conducting layer and the second conducting layer are electrically connected to the first pad and the second pad, respectively.

10. The chip package as claimed in claim 9, wherein a light emerging surface of the light emitting chip has a normal vector substantially parallel to a normal vector of the surface of the circuit board.

11. The chip package as claimed in claim 9, wherein a light emerging surface of the light emitting chip has a normal vector substantially perpendicular to a normal vector of the surface of the circuit board.

12. A method for forming a chip package, comprising:

providing a carrier wafer comprising a plurality of regions defined by a plurality of predetermined scribe lines;

forming a plurality of through-holes penetrating through an upper surface and an opposite lower surface of the carrier wafer on locations of the predetermined scribe lines;

forming a conducting material layer overlying the carrier wafer, wherein the conducting material layer is extended to overly the sidewalls of the through-holes;

patterning the conducting material layer into a plurality of conducting layers which are separated from each other and do not contact with the predetermined scribe lines;

providing a plurality of chips each having a first electrode and a second electrode;

respectively disposing the chips on the corresponding regions, wherein at least one of the chips is disposed on each of the regions, and the first electrode and the second electrode of each of the chips are electrically connected to two of the conducting layers in the regions where the chips are located, respectively; and

dicing the carrier wafer along the predetermined scribe lines to separate a plurality of chip packages.

13. The method for forming a chip package as claimed in claim 12, wherein the step for forming the through-holes comprises:

forming a plurality of holes which extend from the upper surface toward the lower surface of the carrier wafer on the locations of the predetermined scribe lines; and

thinning the carrier wafer from the lower surface to expose the holes.

14. The method for forming a chip package as claimed in claim 13, further comprising forming a plurality of recesses in the carrier wafer, wherein the recesses extend from the upper surface toward the lower surface, and the chips are correspondingly disposed on bottom portions of the recesses, respectively.

15. The method for forming a chip package as claimed in claim 14, wherein the recesses and the holes are formed simultaneously.

16. The method for forming a chip package as claimed in claim 12, further comprising forming an insulating layer between the conducting layer and the carrier wafer.

17. The method for forming a chip package as claimed in claim 12, wherein the chips comprise a light emitting chip.

18. The method for forming a chip package as claimed in claim 17, further comprising:

providing a circuit board having a first pad and a second pad located on a surface of the circuit board; and

disposing one of the chip packages on the circuit board such that the first electrode and the second electrode of the chip package are electrically connected to the first pad and the second pad, respectively.

19. The method for forming a chip package as claimed in claim 18, wherein a normal vector of the surface of the circuit board is substantially parallel to a normal vector of a light emerging surface of the chip.

20. The method for forming a chip package as claimed in claim 18, wherein a normal vector of the surface of the circuit board is substantially perpendicular to a normal vector of a light emerging surface of the chip.