NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, SIGNAL PROCESSING SYSTEM, METHOD FOR CONTROLLING SIGNAL PROCESSING SYSTEM, AND METHOD FOR REPROGRAMMING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20110170346A1
• Filed: 03/23/2011
• Published: 07/14/2011
• Est. Priority Date: 10/05/2009
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Mori, Toshiki, NAGAI, Hiroyasu, Toki, Masahiro
• Application Number:
  US13/070,276
• Publication Number:
  US 20110170346A1
• Time in Patent Office: Days
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A non-volatile semiconductor memory device includes a memory cell array including a data storage area and a reprogram information storage area, and a reprogram information holder circuit configured to store data read from the reprogram information storage area. A reference level switch circuit selects one from a plurality of read reference levels generated by a reference level generator circuit, based on an output of the reprogram information holder circuit. A read circuit reads memory cell data from the data storage area 104 based on the selected read reference level, and outputs the memory cell data. Therefore, a degradation in data hold capability due to reprogram operation is reduced or prevented. In addition, intended operation is achieved without being affected by interruption or resumption of power supply, a circuit size is reduced, and high-speed read operation is achieved.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information;

a read circuit configured to determine a memory cell storage state of the memory cell array;

a reprogram information holder configured to store data read from the reprogram information storage area;

a first read reference signal configured to determine a memory cell storage state of the data storage area in which a first storage state is stored as a first logic value and a second storage state is stored as a second logic value;

a second read reference signal configured to determine a memory cell storage state of the data storage area in which the first and second storage states are stored as a first logic value and a third storage state is stored as a second logic value; and

a read reference signal selector configured to select and output one of the first and second read reference signals to the read circuit, based on an output of the reprogram information holder.

4. The non-volatile semiconductor memory device of claim 1, wherein

the first state is an erase level state and the second state is a first program level state, and

the third state is a second program level state which is different from the first program level state.

5. The non-volatile semiconductor memory device of claim 1, wherein

the first logic value has a logic 1 and the second logic value has a logic 0.

6. The non-volatile semiconductor memory device of claim 1, wherein

the first logic value has a logic 0 and the second logic value has a logic 1.

7. The non-volatile semiconductor memory device of claim 1, wherein

the reprogram information holder includes a register configured to store data read from the reprogram information storage area.

8. The non-volatile semiconductor memory device of claim 1, wherein

the read reference signal selector includes a switch configured to be controlled based on an output of the reprogram information holder.

15. The non-volatile semiconductor memory device of claim 1, wherein

the plurality of storage states of each memory cell are a plurality of threshold values.

16. The non-volatile semiconductor memory device of claim 1, wherein

the plurality of storage states of each memory cell are a plurality of resistance values.

17. The non-volatile semiconductor memory device of claim 1, wherein

the read reference signal indicates a read reference current value.

2. A non-volatile semiconductor memory device comprising:

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information;

a first read circuit configured to determine a memory cell storage state of the data storage area;

a first read reference signal configured to determine a memory cell storage state of the data storage area in which a first storage state is stored as a first logic value and a second storage state is stored as a second logic value;

a second read reference signal configured to determine a memory cell storage state of the data storage area in which the first and second storage states are stored as a first logic value and a third storage state is stored as a second logic value;

a second read circuit configured to determine a state of the reprogram information storage area; and

a read reference signal selector configured to select and output one of the first and second read reference signals to the first read circuit, based on an output of the second read circuit.

9. The non-volatile semiconductor memory device of claim 2, wherein

the read reference signal selector includes a switch configured to be controlled based on the output of the second read circuit.

3. A non-volatile semiconductor memory device comprising:

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information;

a first and a second read circuit configured to determine a memory cell storage state of the data storage area;

a reprogram information holder configured to store data read from the reprogram information storage area;

a first read reference signal configured to be input to the first read circuit to determine a memory cell storage state of the data storage area in which a first storage state is stored as a first logic value and a second storage state is stored as a second logic value; and

a second read reference signal configured to be input to the second read circuit to determine a memory cell storage state of the data storage area in which the first and second storage states are stored as a first logic value and a third storage state is stored as a second logic value,

wherein

one of outputs of the first and second read circuits is selected to output data read from at least one of the plurality of memory cells of the data storage area, based on an output of the reprogram information holder.

10. The non-volatile semiconductor memory device of claim 3, further comprising:

a selector configured to select one of the outputs of the first and second read circuits based on the output of the reprogram information holder.

11. A non-volatile semiconductor memory device comprising:

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information;

a read circuit configured to determine a memory cell storage state of the memory cell array;

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells of the data storage area and a control signal configured to control operation timing;

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode;

a control circuit configured to receive the control command signal and control internal operation;

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state,

a plurality of read reference signals configured to read a memory cell storage state of the data storage area; and

a read reference signal selector configured to selectively output the plurality of read reference signals to the read circuit,

wherein

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read reference signals, and outputs the state signal indicating the control command receive ready state.

27. The non-volatile semiconductor memory device of claim 11, wherein the plurality of storage states of each memory cell are a plurality of threshold values.

28. The non-volatile semiconductor memory device of claim 11, wherein the plurality of storage states of each memory cell are a plurality of resistance values.

29. The non-volatile semiconductor memory device of claim 11, wherein the read reference signal indicates a read reference current value.

12. A non-volatile semiconductor memory device comprising:

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information;

a plurality of read reference signals configured to read a memory cell storage state of the data storage area;

a plurality of read circuits configured to receive the plurality of read reference signals to determine the memory cell storage state of the data storage area;

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells of the data storage area and a control signal configured to control operation timing;

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode;

a control circuit configured to receive the control command signal and control internal operation; and

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state, wherein

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read circuits, and outputs the state signal indicating the control command receive ready state.

13. A signal processing system comprising:

a non-volatile semiconductor memory device; and

a processor,

wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information,

a read circuit configured to determine a memory cell storage state of the memory cell array,

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells of the data storage area and a control signal configured to control operation timing,

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode,

a control circuit configured to receive the control command signal and control internal operation,

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state,

a plurality of read reference signals configured to read a memory cell storage state of the data storage area, and

a read reference signal selector configured to selectively output the plurality of read reference signals to the read circuit,

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read reference signals, and outputs the state signal indicating the control command receive ready state, and

the processor includes

a signal terminal configured to output the address signal and the control signal to the non-volatile semiconductor memory device,

a signal terminal configured to receive and output data, and output the control command signal, and

a signal terminal configured to receive the state signal, and

the processor outputs the erase command to the non-volatile semiconductor memory device, reads the state signal of the non-volatile semiconductor memory device, and determines whether or not erase operation with respect to the non-volatile semiconductor memory device has been completed.

18. The signal processing system of claim 13, wherein

the state signal is a ready/busy signal which indicates whether the non-volatile semiconductor memory device is operating or is ready to receive a control command, and is output to a specific signal terminal.

19. The signal processing system of claim 13, wherein

the state signal is a data polling signal which is output, to a data terminal, as a signal indicating whether the non-volatile semiconductor memory device is operating or has completed operation.

14. A signal processing system comprising:

a non-volatile semiconductor memory device; and

a processor,

wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information,

a plurality of read reference signals configured to read a memory cell storage state of the data storage area,

a plurality of read circuits configured to receive the plurality of read reference signals to determine the memory cell storage state of the data storage area,

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells of the data storage area and a control signal configured to control operation timing,

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode,

a control circuit configured to receive the control command signal and control internal operation, and

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state, and

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read circuits, and outputs the state signal indicating the control command receive ready state, and

the processor includes

a signal terminal configured to output the address signal and the control signal to the non-volatile semiconductor memory device,

a signal terminal configured to receive and output data, and output the control command signal, and

a signal terminal configured to receive the state signal, and

the processor outputs the erase command to the non-volatile semiconductor memory device, reads the state signal of the non-volatile semiconductor memory device, and determines whether or not erase operation with respect to the non-volatile semiconductor memory device has been completed.

20. A method for controlling a signal processing system comprising a non-volatile semiconductor memory device and a processor, wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information, where the memory cell array is divided into a plurality of erase units,

a read circuit configured to determine a state of at least one of the plurality of memory cells,

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells, and a control signal configured to control operation timing,

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode,

a control circuit configured to receive the control command signal and control internal operation,

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state,

a plurality of read reference signals configured to read data stored in at least one of the plurality of memory cells, and

a read reference signal selector configured to selectively output the plurality of read reference signals to the read circuit, and

the processor includes

a signal terminal configured to output the address signal and the control signal to the non-volatile semiconductor memory device,

a signal terminal configured to receive and output data, and output the control command signal, and

a signal terminal configured to receive the state signal, and

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read reference signals, and outputs the state signal indicating the control command receive ready state, and

the processor reads reprogram information of a first erase unit from the non-volatile semiconductor memory device, and if it is necessary to change a storage state of at least one of the plurality of memory cells in the first erase unit when outputting an erase command, outputs the erase command with respect to a second erase unit which is different from the first erase unit.

22. The method of claim 20, wherein

the processor, after outputting a program command with respect to the second erase unit, reads the state signal of the non-volatile semiconductor memory device, and if the state signal indicates the control command receive ready state, erases the first erase unit into an initial state.

23. The method of claim 20, wherein

the plurality of erase units are N different erase units, where N is two or more, and

the processor outputs a program command with respect to one of the N erase units.

21. A method for controlling a signal processing system comprising a non-volatile semiconductor memory device and a processor, wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information, where the memory cell array is divided into a plurality of erase units,

a plurality of read reference signals configured to read data stored in at least one of the plurality of memory cells,

a plurality of read circuits configured to receive the plurality of read reference signals to determine a state of at least one of the plurality of memory cells,

a signal terminal configured to receive an address signal configured to identify at least one of the plurality of memory cells, and a control signal configured to control operation timing,

a signal terminal configured to receive and output data, and receive a control command signal configured to set an operating mode,

a control circuit configured to receive the control command signal and control internal operation,

a signal terminal configured to output a state signal indicating whether the internal operation is being performed or is in a control command receive ready state, and

a read reference signal selector configured to selectively output the plurality of read reference signals to the plurality of read circuits, and

the processor includes

a signal terminal configured to output the address signal and the control signal to the non-volatile semiconductor memory device,

a signal terminal configured to receive and output data, and output the control command signal, and

a signal terminal configured to receive the state signal, and

the non-volatile semiconductor memory device, when receiving an erase command as the control command signal, selectively switches the plurality of read circuits, and outputs the state signal indicating the control command receive ready state, and

the processor reads reprogram information of a first erase unit from the non-volatile semiconductor memory device, and if it is necessary to change a storage state of at least one of the plurality of memory cells in the first erase unit when outputting an erase command, outputs the erase command with respect to a second erase unit which is different from the first erase unit.

24. A method for reprogramming a non-volatile semiconductor memory device, wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information,

a read circuit configured to determine a memory cell storage state of the data storage area, and

a plurality of read reference signals, and

read operation is performed using the plurality of read reference signals,

when reprogram operation is performed in a first data state in which a first logic value or a second logic value is written in the data storage area,

then if information in the reprogram information storage area indicates that the number of reprogram operations is less than a predetermined value, reprogram information obtained by adding one to the number of reprogram operations is written to the reprogram information storage area, and based on the information indicating the number of reprogram operations stored in the reprogram information storage area, the plurality of read reference signals are selected, and data is written to a second data state different from the first data state, or

then if the information in the reprogram information storage area indicates the predetermined value, the data storage area and the reprogram information storage area are erased, and based on the information indicating the number of reprogram operations stored in the reprogram information storage area, one is selected from the plurality of read reference signals, and with reference to the selected read reference signal, data is written into a second data state which is different from the first data state, and

the predetermined value is set in association with the number of the plurality of possible read reference signals.

26. The method of claim 24, wherein

the plurality of read reference signals are M different read reference signals, where M is two or more,

the selection of the plurality of read reference signals is selection of a specific one from the M read reference signals,

the data states are M different data states, where M is two or more, and

in the program operation, data is written into one of the M data states.

25. A method for reprogramming a non-volatile semiconductor memory device, wherein

the non-volatile semiconductor memory device includes

a memory cell array including a data storage area including a plurality of memory cells having a plurality of possible storage states and a reprogram information storage area configured to store reprogram information,

a high-speed program mode signal terminal,

a read circuit configured to determine a memory cell storage state of the data storage area, and

a plurality of read reference signals, and

read operation is performed using the plurality of read reference signals,

when reprogram operation is performed in a first data state in which a first logic value or a second logic value is written in the data storage area,

then if information in the reprogram information storage area is less than a first setting value and the high-speed program mode signal terminal is valid, reprogram information obtained by adding one to the number of reprogram operations is written to the reprogram information storage area, and based on the information indicating the number of reprogram operations stored in the reprogram information storage area, one is selected from the plurality of read reference signals, and with reference to the selected read reference signal, data is written into a second data state different from the first data state, or

then if the information in the reprogram information storage area is not less than the first setting value or the high-speed program mode signal terminal is invalid,

then if the information in the reprogram information storage area is less than a second setting value, reprogram information obtained by adding one to the number of reprogram operations is written to the reprogram information storage area, and based on the information indicating the number of reprogram operations stored in the reprogram information storage area, one is selected from the plurality of read reference signals, and with reference to the selected read reference signal, data is written into the second data state different from the first data state, or

then if the information in the reprogram information storage area is the second setting value, the data storage area and the reprogram information storage area are erased, and based on the information indicating the number of reprogram operations stored in the reprogram information storage area, one is selected from the plurality of read reference signals, and with reference to the selected read reference signal, data is written into the second data state different from the first data state, and

the first and second predetermined values are set in association with the plurality of possible read reference signals, and the first predetermined value is greater than the second predetermined value.