NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES

• US 20110170352A1
• Filed: 03/28/2011
• Published: 07/14/2011
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 8,582,372 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

Claims

1. A NAND Flash memory comprising:

at least two well sectors each selectively eraseable in response to an erase voltage;

at least one NAND cell string in each of the at least two well sectors; and

,

a bitline electrically coupled to the at least one NAND cell string in each of the at least two well sectors.

2. A method for erasing a memory block in a NAND flash device, comprising:

applying an erase voltage to a first well sector containing a first NAND cell string connected to a bitline for erasing memory cells of the first NAND cell string; and

,

inhibiting application of the erase voltage to a second well sector containing a second NAND cell string connected to the bitline.

3. A NAND flash memory device, comprising:

a memory array having at least two well sectors, each of the two well sectors including NAND cell strings;

a charge pump for generating an erase voltage; and

,

a selector for selectively passing the erase voltage to one of the at least two well sectors.