High Speed Switch With Data Converter Physical Ports And Processing Unit

• US 20110170619A1
• Filed: 06/11/2010
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Anvari, Kiomars
• Granted Patent: US 8,503,515 B2
• Time in Patent Office: Days
• US Class Current: 375/259
• CPC Class Codes: H04L 12/40169 Flexible bus arrangements arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654

Abstract

An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

Claims

1. A communication system comprising:

an integrated circuit chip that includes;

a switch fabric;

control logic that controls the transmission of digital signals through the switch fabric;

a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device;

a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and

a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

2. The communication system of claim 1, further comprising a control processor coupled to the control logic, wherein the control processor controls off-chip circuitry coupled to the data converter physical interface in response to digital signals received from the transceiver block.

3. The communication system of claim 2, wherein the off-chip circuitry comprises an analog receiver circuit, which is coupled to the data converter physical interface.

4. The communication system of claim 3, wherein the off-chip circuitry further comprises an analog transmitter circuit, which is coupled to the data converter physical interface.

5. The communication system of claim 1, further comprising a remote device, external to the integrated circuit chip, wherein the remote device is coupled to one of the transceivers of the transceiver block, wherein digital signals received from the data converter physical interface are transmitted to the remote device.

6. The communication system of claim 5, wherein the control logic transmits digital signals received from the data converter physical interface to the remote device during predetermined time windows.

7. The communication system of claim 5, wherein the control logic transmits digital signals received from the data converter physical interface to the remote device in response to requests generated by the remote device.

8. The communication system of claim 5, further comprising a baseband processor, external to the integrated circuit chip, wherein the baseband processor is coupled to one of the transceivers of the transceiver block, wherein digital signals received from the data converter physical interface are transmitted to both the remote device and the baseband processor in parallel.

9. The communication system of claim 1, further comprising a remote device, external to the integrated circuit chip, wherein the remote device is coupled to one of the transceivers of the transceiver block, wherein digital signals transmitted to the data converter physical interface are transmitted to the remote device in parallel.

10. The communication system of claim 9 wherein the digital signals are transmitted to the remote device during predetermined time windows.

11. The communication system of claim 9, wherein the digital signals are transmitted to the remote device in response to requests generated by the remote device.

12. The communication system of claim 9, further comprising:

a plurality of analog signal processing circuits coupled to the data converter physical interface; and

a redundancy circuit for replacing a defective one of the analog signal processing circuits, wherein the redundancy circuit is controlled by the signal processing engine.

13. The communication system of claim 1, wherein the data converter physical interface comprises an analog-to-digital (A/D) physical interface comprising one or more analog-to-digital converters (ADCs), each converting an analog input signal received from an external source into digital signals that are transmitted to the control logic and routed through the switch fabric.

14. The communication system of claim 1, wherein the data converter physical interface comprises a digital-to-analog (D/A) physical interface comprising one or more digital-to-analog converters (DACs), each converting digital signals received from the control logic into an analog output signal that is transmitted to a corresponding external destination.

15. A method of operating a switch in a communication system comprising:

receiving a serial data input signal on a first physical port of the switch;

converting the serial data input signal to a parallel data input signal at the first physical port of the switch, wherein the first physical port implements a serial data protocol;

routing the parallel data input signal to a processing block of the switch, wherein the processing block processes the parallel data input signal to provide a parallel data output signal;

routing the parallel data output signal through a switch fabric of the switch to a second physical port of the switch; and

converting the parallel data input signal into a serial data output signal at the second physical port of the switch, wherein the first and second physical ports, the processing block and the switch fabric are located on the same integrated circuit chip.

16. The method of claim 15, further comprising performing an analog-to-digital conversion in the first physical port of the switch.

17. The method of claim 15, further comprising performing a digital-to-analog conversion in the second physical port of the switch.

18. The method of claim 15, further comprising:

generating a control signal with the processing unit in response to the parallel data input signal; and

using the control signal to adjust a receiver circuit coupled to the first physical port of the switch.

19. The method of claim 15, further comprising:

generating a control signal with the processing unit in response to the parallel data input signal; and

using the control signal to adjust a transmitter circuit coupled to the second physical port of the switch.

20. The method of claim 15, further comprising

routing the parallel data output signal through the switch fabric to a third physical port of the switch;

and

transmitting the parallel data output signal from the third physical port of the switch to an external device; and

monitoring the parallel data output signal with the external device.

21. The method of claim 20, further comprising transmitting the parallel data output signal from the third physical port of the switch to the external device in response to a request from the external device.

22. The method of claim 20, further comprising transmitting the parallel data output signal from the third physical port of the switch to the external device during predetermined time windows.

23. The method of claim 15, further comprising:

monitoring the parallel data input signal with the processing unit to determine whether the parallel data input signal is valid; and

switching the serial data input signal from the first physical port to a third physical port upon determining that the parallel data input signal is not valid.

24. The method of claim 15, further comprising:

monitoring the serial data output signal with the processing unit to determine whether the serial data output signal is valid; and

switching the serial data output signal from the second physical port to a third physical port upon determining that the serial data output signal is not valid.