Three Dimensional Integration With Through Silicon Vias Having Multiple Diameters

• US 20110171582A1
• Filed: 01/14/2010
• Published: 07/14/2011
• Est. Priority Date: 01/14/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kei, Ramona, Lisi, Anthony D., Wise, Richard, Farooq, Mukta G., Kinser, Emily R., Yusuff, Hakeem
• Granted Patent: US 8,399,180 B2
• Time in Patent Office: Days
• US Class Current: 430/314
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

Claims

1. A method comprising:

patterning a photoresist layer on a substrate of a structure;

removing a first portion of the photoresist layer to expose a first area of the substrate;

etching the first area to form a cavity having a first depth;

removing a second portion of the photoresist to expose an additional area of the substrate; and

etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

2. The method of claim 1, wherein the structure includes a first wafer component arranged on a second wafer component.

3. The method of claim 2, wherein first wafer component has a substrate portion and a wiring level portion arranged on a wiring level portion of second wafer component.

4. The method of claim 1, wherein the structure includes a first chip component arranged on a second chip component.

5. The method of claim 1, wherein the substrate includes a silicon material.

6. The method of claim 1, wherein the removal of the second portion of the photoresist layer to expose an additional area of the substrate is performed in-situ.

7. The method of claim 1, wherein the photoresist layer is patterned on an exposed silicon surface of the structure.

8. The method of claim 1, wherein after etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure the method further comprises:

forming a dielectric layer in the cavity;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric;

filling the second cavity with a conductive material; and

removing the excess conductive material by planarization.

9. The method of claim 3, wherein the wiring level portion of the first wafer component and the wiring level portion of the second wafer component are bonded together with an adhesive.

10. The method of claim 3, wherein the wiring level portion of the first wafer component and the wiring level portion of the second wafer component are bonded together with a metal.

11. The method of claim 8, wherein the conductive material is operative to electrically connect the first conductor and the second conductor.

12. A method comprising:

patterning a photoresist layer on a substrate of a structure, the photoresist layer defining an opening having a first area;

etching to form a cavity having a first depth in the structure partially defined by the first area;

depositing a spacer material along sidewalls of the cavity and forming an opening having a second area in said spacer material; and

etching said cavity and said second area to increase the depth of a portion of the cavity in the structure to expose a first conductor and a second conductor in the structure.

13. The method of claim 12, wherein the structure includes a first wafer component arranged on a second wafer component.

14. The method of claim 13, wherein first wafer component has a substrate portion and a wiring level portion arranged on a wiring level portion of the second wafer component.

15. The method of claim 12, wherein the substrate includes a silicon material.

16. The method of claim 12, wherein the depositing the spacer material along sidewalls of the cavity to define an opening having a second area is performed in-situ.

17. The method of claim 12, wherein the photoresist layer is deposited on a silicon layer of the first wafer component.

18. The method of claim 12, wherein the structure further includes a hardmask layer deposited on a top silicon layer, and the photoresist layer is deposited on the hardmask layer.

19. The method of claim 12, wherein the method further comprises:

removing the photoresist layer;

removing the spacer material;

forming a dielectric layer in the cavity;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric layer;

filling the cavity with a conductive material; and

removing the excess conductive material by planarization.

20. The method of claim 19, wherein the conductive material is operative to electrically connect the first conductor and the second conductor.