REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD

• US 20110171756A1
• Filed: 03/25/2011
• Published: 07/14/2011
• Est. Priority Date: 04/29/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: KATOPIS, George A., WEBB, Bucknell C., ANDRY, Paul S., TSAPEPAS, Stelios G., KNICKERBOCKER, John U., BUCHWALTER, Stephen L.
• Granted Patent: US 8,227,264 B2
• Time in Patent Office: Days
• US Class Current: 438/4
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

Abstract

An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Claims

1. A method of fabricating an electronic device assembly, the method comprising:

coupling an interposer to a substrate, the substrate comprising a first material having a first thermal expansivity, and the interposer comprising a second material having a second thermal expansivity, wherein the second thermal expansivity is different from the first thermal expansivity, and there is a coefficient of thermal expansion mismatch between the first material of the substrate and the second material of the interposer, and wherein the coupling comprises providing a first plurality of electrical contacts and an adhesive material at least partially surrounding the first plurality of electrical contacts to couple the interposer to the substrate, the adhesive material bonding the interposer to the substrate and reducing strain on the first plurality of electrical contacts resulting from the coefficient of thermal expansion mismatch between the second material of the interposer and the first material of the substrate;

coupling an integrated circuit chip to the interposer using a second plurality of electrical contacts, wherein the integrated circuit chip is coupled to the interposer without use of an adhesive material at least partially surrounding the second plurality of electrical contacts, and wherein the integrated circuit chip comprises the second material having the second thermal expansivity, and the second plurality of electrical contacts have a lower reworking temperature than the first plurality of electrical contacts, and wherein the second plurality of electrical contacts coupling the integrated circuit chip to the interposer without use of adhesive facilitates reworking of the electronic device assembly by facilitating removal of the integrated circuit chip from the interposer at the lower reworking temperature of the second plurality of electrical contacts.

2. The method of claim 1, further comprising removing the integrated circuit chip from the interposer if the integrated circuit chip is defective, and coupling another integrated circuit chip to the interposer employing only a third plurality of electrical contacts without use of adhesive material at least partially surrounding the third plurality of conductive contacts.

3. The method of claim 1, wherein the interposer comprises electrical vias extending from a first main surface to a second main surface thereof and electrically connecting at least some contacts of the second plurality of electrical contacts to at least some contacts of the first plurality of electrical contacts.

4. The method of claim 1, further comprising thinning the integrated circuit chip prior to coupling the integrated circuit chip to the interposer, wherein the interposer comprises a first thickness and the integrated circuit chip comprises a second thickness, the second thickness being greater than the first thickness.

5. The method of claim 1, wherein the integrated circuit chip is a first, thinned integrated circuit chip, and wherein the method further comprises coupling a second, thinned integrated circuit chip to the first thinned, integrated circuit chip via a third plurality of electrical contacts only, without use of adhesive material at least partially surrounding the third plurality of electrical contacts, the third plurality of electrical contacts being reworkable at a lower temperature than the first plurality of electrical contacts.

6. The method of claim 5, wherein the third plurality of electrical contacts are reworkable at a lower temperature than the first plurality of electrical contacts.

7. The method of claim 1, wherein the interposer comprises a first thickness and the integrated circuit chip comprises a second thickness, the second thickness being greater than the first thickness.

8. The method of claim 7, wherein the first thickness of the interposer is one third or less the second thickness of the integrated circuit chip.