Methods of Making a Semiconductor Memory Device

• US 20110171802A1
• Filed: 03/25/2011
• Published: 07/14/2011
• Est. Priority Date: 09/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Haller, Gordon, Tang, Sanh D., Doyle, Daniel H.
• Granted Patent: US 8,446,762 B2
• Time in Patent Office: Days
• US Class Current: 438/294
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Claims

1-40. -40. (canceled)

41. A method for making a semiconductor memory device, the method comprising:

forming isolation regions in semiconductor material;

removing portions of the semiconductor material between the isolation regions to form a floating body semiconductor material island and to form a void beneath the island over unremoved semiconductor material;

forming a bias gate within the void;

forming a field effect transistor gate over the floating body semiconductor material island; and

forming source/drain regions operatively proximate the field effect transistor gate.

42. The method of claim 41 comprising forming a bias gate void in the bias gate.

43. The method of claim 42 comprising forming the bias gate void to extend from one isolation region to another isolation region.

44. The method of claim 41 comprising forming the field effect transistor gate to be recessed within the floating body semiconductor material island.

45. The method of claim 41 comprising forming a dummy gate over the respective isolation regions.

46. The method of claim 45 comprising forming the field effect transistor gate to be recessed within the floating body semiconductor material island.

47. The method of claim 45 comprising forming the dummy gate and the field effect transistor gate at the same time.

48. The method of claim 41 wherein forming the field effect transistor gate comprises depositing and subsequently recessing conductive material.

49. The method of claim 41 comprising providing gate dielectric above the bias gate, the gate dielectric being formed before forming the bias gate.

50. The method of claim 41 comprising providing gate dielectric above and below the bias gate, the gate dielectric being formed before forming the bias gate.

51. The method of claim 41 comprising forming a cap over the semiconductor material prior to said removing.

52. The method of claim 51 comprising forming the cap to extend between and contact the isolation regions.

53. The method of claim 41 wherein the removing comprises etching the semiconductor material.

54. The method of claim 53 wherein the etching comprises a trench etch followed by an undercut etch.

55. A method for making a transistor, comprising:

forming laterally opposing isolation regions in semiconductor material;

laterally supporting a channel region of the transistor above a void in the semiconductor material by lateral engagement of the channel region with the laterally opposing isolation regions while forming conductive material below the channel region within the void;

forming a field effect transistor gate over the channel region; and

forming source/drain regions operatively proximate the field effect transistor gate.

56. The method of claim 55 wherein the conductive material comprises a bias gate.

57. The method of claim 56 comprising laterally supporting the channel region of the transistor above the void by lateral engagement of the channel region with the laterally opposing isolation regions while forming a gate dielectric prior to forming the conductive material of the bias gate.

58. A method for making a transistor, comprising:

forming laterally opposing isolation regions in semiconductor material;

elevationally supporting a channel region of the transistor above a void in the semiconductor material by engagement of the channel region with an overlying cap while forming conductive material below the channel region within the void;

forming a field effect transistor gate over the channel region; and

forming source/drain regions operatively proximate the field effect transistor gate.

59. The method of claim 58 comprising forming laterally opposing isolation regions in the semiconductor material, the cap extending between and contacting the laterally opposing isolation regions.

60. The method of claim 58 comprising forming laterally opposing isolation regions in the semiconductor material, and laterally supporting the channel region of the transistor above the void by lateral engagement of the channel region with the laterally opposing isolation regions while forming the conductive material below the channel region within the void.

61. The method of claim 60 wherein the cap extends between and contacts the laterally opposing isolation regions.

62. The method of claim 58 wherein the conductive material comprises a bias gate.

63. The method of claim 62 comprising elevationally supporting the channel region of the transistor above the void by engagement of the channel region with the overlying cap while forming a gate dielectric prior to forming the conductive material of the bias gate.

64. A method for making a semiconductor memory device comprising a field effect transistor, a floating body region, and a bias gate below the floating body region, the method comprising forming the bias gate after forming the floating body region.

65. A method for making a semiconductor memory device comprising a field effect transistor, a floating body region, a bias gate below the floating body region, and gate dielectric below the bias gate and between the bias gate and the floating body region, the method comprising forming the gate dielectric below the bias gate prior to forming the bias gate.

66. A method for making a semiconductor memory device comprising a field effect transistor, a floating body region, a bias gate below the floating body region, and gate dielectric below the bias gate and between the bias gate and the floating body region, the method comprising forming the gate dielectric between the bias gate and the floating body region prior to forming the bias gate.

67. The method of claim 66 comprising forming the gate dielectric below the bias gate prior to forming the bias gate.