EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION

• US 20110172984A1
• Filed: 03/19/2010
• Published: 07/14/2011
• Est. Priority Date: 01/08/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tian, Shurong, Schuelke, Brian A., Gara, Alan, Coteus, Paul W., Kursun, Eren, Cher, Chen-Yong, Paulsen, David P., Sheets, John E. II
• Granted Patent: US 8,571,847 B2
• Time in Patent Office: Days
• US Class Current: 703/21
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

Claims

1. A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising:

conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a first output corresponding to a first multi-core processor core to turn off;

conducting a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes a second output corresponding to a second multi-core processor core to turn off;

comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output;

outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

2. The method of claim 1, further comprising turning off a core of the multi-processor corresponding to the third output.

3. The method of claim 1, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a static multi-core processor analysis conducted under the absence of variation and a first result of the static processor analysis is output and wherein an occurrence of a variation pattern is simulated on the first result and a second result is output and wherein the second result quantifies the occurrence of the variation pattern on the first result and the second result is output via a signal.

4. The method of claim 3, wherein the variation pattern is selected from a library of variation patterns and wherein the second result is output into a data structure.

5. The method of claim 4, wherein the data structure performs the function of a look-up table.

6. The method of claim 3, wherein the static multi-core processor analysis takes into consideration at least one of the following:

a thermal characteristic of the multi-core processor, a power characteristic of the multi-core processor and a performance characteristic of the multi-core processor.

7. The method of claim 1, wherein the multi-core processor has a plurality of power modes.

8. The method of claim 3, wherein the variation pattern includes data corresponding to at least one of the following:

process variation, packaging, cooling, power delivery and power distribution.

9. The method of claim 1, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage is conducted during at least one of the following:

a wafer-level test and a module-level test; and

wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes assessing variation of each core of the multi-core processor by at least one of the following;

a variation tester, a ring oscillator and a temperature sensor.

10. A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising:

determining via a simulation a condition for core turn-off at a design stage for a certain core of the multi-core processor;

assessing whether the condition matches to an actual variation in the certain core, the actual variation measured at a testing stage for the certain core;

providing a static core turn-off list based on the matching of the condition and the actual variation in the certain core;

selecting a core of the multi-core processor to turn off based on the contents of the static turn-off list.

11. The method of claim 10, wherein the determining step includes a static multi-core processor analysis conducted under the absence of variation and a first result of the static multi-core processor analysis is output and wherein an occurrence of a variation pattern is simulated on the first result and a second result is output into a data structure and wherein the second result quantifies the occurrence of the variation pattern on the first result.

12. The method of claim 11, wherein the data structure performs the function of a look-up table.

13. The method of claim 12, wherein the multi-core processor has a plurality of power modes and wherein the static multi-core processor analysis takes into consideration at least one of the following:

a thermal characteristic of the multi-core processor, a power characteristic of the multi-core processor and a performance characteristic of the multi-core processor.

14. The method of claim 11, wherein the variation pattern includes data corresponding to at least one of the following:

process variation, packaging, cooling, power delivery and power distribution.

15. The method of claim 13, wherein the actual variation is measured during at least one of the following:

a wafer final test and module final test; and

wherein the actual variation is measured by at least one of the following;

a variation tester, a ring oscillator and a temperature sensor.

16. A computer system for improving efficiency of a static core turn-off in a multi-core processor with variation, the system comprising:

a memory;

a processor in communications with the computer memory, wherein the computer system is capable of performing a method comprising;

conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a first output corresponding to a first multi-core processor core to turn off;

conducting a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes a second output corresponding to a second multi-core processor core to turn off;

comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output;

outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

17. The computer system of claim 16, further comprising turning off a core of the multi-processor corresponding to the third output.

18. The computer system of claim 16, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a static multi-core processor analysis conducted under the absence of variation and a first result of the static processor analysis is output and wherein an occurrence of a variation pattern is simulated on the first result and a second result is output and wherein the second result quantifies the occurrence of the variation pattern on the first result and the second result is output via a signal into a data structure and wherein the variation pattern is selected from a library of variation patterns.

19. The computer system of claim 18, wherein the data structure performs the function of a look-up table.

20. The computer system of claim 18, wherein the static multi-core processor analysis takes into consideration at least one of the following:

a thermal characteristic of the multi-core processor, a power characteristic of the multi-core processor and a performance characteristic of the multi-core processor.

21. The computer system of claim 18, wherein the multi-core processor has a plurality of power modes and wherein the turn-off analysis of the multi-core at the multi-core processor'"'"'s testing stage is conducted during at least one of the following:

a wafer final test and a module final test; and

wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes assessing variation of each core of the multi-core processor by at least one of the following;

a variation tester, a ring oscillator and a temperature sensor.

22. A computer program product for improving efficiency of a static core turn-off in a multi-core processor with variation, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a first output corresponding to a first multi-core processor core to turn off;

conducting a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes a second output corresponding to a second multi-core processor core to turn off;

comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output;

outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

23. The computer program product of claim 22, further comprising turning off a core of the multi-processor corresponding to the third output and wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a static multi-core processor analysis conducted under the absence of variation and a first result of the static multi-core processor analysis is output and wherein an occurrence of a variation pattern is simulated on the first result and a second result is output wherein the second result quantifies the occurrence of the variation pattern on the first result and the second result is output via a signal into a data structure and wherein the data structure performs the function of a look-up table and wherein the variation pattern is selected from a library of variation patterns.

24. The computer program of claim 22, wherein the multi-core processor has a plurality of power modes and wherein the static multi-core processor analysis takes into consideration at least one of the following:

a thermal characteristic of the multi-core processor, a power characteristic of the multi-core processor and a performance characteristic of the multi-core processor; and

wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage is conducted during at least one of the following;

a wafer final test and a module final test; and

wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes assessing variation of each core of the multi-core processor by at least one of the following;

a variation tester, a ring oscillator and a temperature sensor.

25. A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation and a plurality of power modes, the method comprising:

using a first output of conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes the first output corresponding to a first multi-core processor core to turn off and wherein the first output is stored in a data structure performing the function of a look-up table;

conducting a turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes a second output corresponding to a second multi-core processor core to turn off;

comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output;

outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

26. The method of claim 25, further comprising turning off a core of the multi-processor corresponding to the third output and wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage is conducted during at least one of the following:

a wafer-level test and a module-level test; and

wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s testing stage includes assessing variation of each core of the multi-core processor by at least one of the following;

a variation tester, a ring oscillator and a temperature sensor.

27. The method of claim 26, wherein the turn-off analysis of the multi-core processor at the multi-core processor'"'"'s design stage includes a static multi-core processor analysis conducted under the absence of variation and a first result of the static multi-core processor analysis is output and wherein an occurrence of a variation pattern is simulated on the first result and a second result is output via a signal and wherein the second result quantifies the occurrence of the variation pattern on the first result.