PROCESSOR SYSTEM WITH AN APPLICATION AND A MAINTENANCE FUNCTION

• US 20110173363A1
• Filed: 02/16/2011
• Published: 07/14/2011
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dahan, Franck, Conti, Gregory
• Granted Patent: US 8,117,367 B2
• Time in Patent Office: Days
• US Class Current: 710/267
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

Claims

1. A processor system with an application and a maintenance function that would interfere with the application if concurrently executed, the processor system comprising

a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output;

a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.

2. The processor system claimed in claim 1 further comprising a memory and wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes memory defragmentation and at least one of said processor cores is operable to launch the memory defragmentation provided an enabling condition exists that any category that uses said memory element is currently in the wait for interrupt mode.

3. The processor system claimed in claim 1 wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes a security integrity check of a secure category on a said processor core, and at least one of said processor cores is operable to launch the security integrity check of that secure category on that processor core provided an enabling condition exists that predetermined public categories are in the wait for interrupt mode.

4. The processor system claimed in claim 1 wherein the processor system is operable to execute plural high-level operating systems (HLOSes), and each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes terminating one HLOS in a particular category on a first of the processor cores and initiating another HLOS on the same processor core, and at least one of said processor cores is operable to launch the other HLOS provided an enabling condition exists that the first processor core activates an interrupt line from the wait for interrupt expansion circuit and signifies that the particular category on the first processor core is in the wait for interrupt mode.

5. The processor system claimed in claim 1 wherein said wait for interrupt expansion circuit is responsive to provide the interrupt signal to a different one of the interrupt inputs depending on which security and context-related modes of a given one of the processors pertain to a wait for interrupt signal therefrom.

6. The processor system claimed in claim 1 further comprising a register, and wherein said wait for interrupt expansion circuit is responsive to the at least one wait for interrupt output to supply a selected portion of said register with a signal representing which of the security and context-related modes of a given one of said processors pertains to a wait for interrupt signal therefrom, said register coupled to at least one of said processors.

7. The processor system claimed in claim 1 wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes an integrity check of a public category, and at least one of said processor cores is operable to launch the integrity check of the public category on that processor core provided an enabling condition exists that the public category is in the wait for interrupt mode.

8. The processor system claimed in claim 1 further comprising a memory and a direct memory access (DMA) process operable in a public category, wherein each processor having a category that issues the wait for interrupt signal is in a wait for interrupt mode relative to that category until interrupted, and the maintenance function includes memory integrity check, and at least one of said processor cores is operable to launch the memory integrity check provided an enabling condition exists that the public category for the DMA process is in the wait for interrupt mode.

9. The processor system claimed in claim 1 further comprising a cellular telephone modem coupled to at least one of said processor cores.

10. The processor system claimed in claim 1 further comprising a digital video broadcast receiving circuit coupled to at least one of said processor cores.

11. The processor system claimed in claim 1 further comprising a digital camera coupled to at least one of said processor cores.