PCI EXPRESS ENHANCEMENTS AND EXTENSIONS

• US 20110173367A1
• Filed: 03/28/2011
• Published: 07/14/2011
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Ajay Bhatt, Anil Vasudevan, Avi Mendelson, David Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Original Assignee: Ajay Bhatt, Anil Vasudevan, Avi Mendelson, David Harriman, Debendra Das Sharma, Doron Shamia, Eliezer Weissmann, Eran Tamari, Ilan Pardo, James Akiyama, Jasmin Ajanovic, Mahesh Wagh, Mark Rosenbluth, Ohad Falik, Peter Barry, Prashant Sethi, Robert Blankenship, Scott Dion Rodgers, Sridhar Muthrasanallur
• Inventors: Das Sharma, Debendra, Shamia, Doron, Barry, Peter, Wagh, Mahesh, Bhatt, Ajay, Blankenship, Robert, Ajanovic, Jasmin, Sethi, Prashant, Muthrasanallur, Sridhar, Pardo, Ilan, Harriman, David, Mendelson, Avi (Abraham), Rodgers, Scott Dion, Rosenbluth, Mark, Akiyama, James, Falik, Ohad, Vasudevan, Anil, Weissmann, Eliezer, Tamari, Eran
• Granted Patent: US 8,099,523 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. A method comprising:

receiving a first packet on a Peripheral Component Interconnect Express (PCIE) interconnect with a first device, wherein the first packet is to include a reference to an address and a plurality of prefetch parameters; and

prefetching an additional element in response to receiving the first packet based on the plurality of prefetch parameters.

2. The method of claim 1, wherein the first packet is a prefetch message, and wherein the prefetch message is also to include an access control hint, the access control hint to be selected from a group consisting of an evict hint, an intent to read only hint, intent to write only hint, intent to read and write hint, and DIO hint.

3. The method of claim 2, wherein the address is a starting address, and wherein the plurality of prefetch parameters are selected from a group consisting of a count, a length, a stride, and a direction.

4. The method of claim 1, further comprising:

determining the additional element to be prefetched based on the starting address and the plurality of prefetch parameters.