Central Repository for Wake-and-Go Mechanism

• US 20110173630A1
• Filed: 02/01/2008
• Published: 07/14/2011
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Granted Patent: US 8,312,458 B2
• Time in Patent Office: Days
• US Class Current: 718/107
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

detecting, by a wake-and-go engine within a multiple processor system, a thread that is waiting for an event associated with a target address;

populating, by the wake-and-go engine, a central repository wake-and-go storage array with the target address;

responsive to detecting that the thread is waiting for the event, placing the thread in a sleep state;

responsive to an event that modifies a data value associated with the target address, determining whether to wake the thread; and

responsive to a determination to wake the thread, placing the thread in a non-sleep state.

2. The method of claim 1, wherein detecting a thread that is waiting for an event associated with a target address comprises recognizing a programming idiom that causes the thread to wait for a data value to be written to the target address.

3. The method of claim 1, wherein determining whether to wake the thread comprises determining whether a data value being written to the target address is a data value for which the thread is waiting.

4. The method of claim 1, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

5. The method of claim 1, wherein the central repository wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

6. The method of claim 1, wherein populating the central repository wake-and-go storage array with the target address comprises recording an entry including at least one of a thread identifier, a central processing unit identifier, a target address, an expected data value, a comparison type, a lock bit, a priority value, or an address of thread state information associated with the thread.

7. The method of claim 6, further comprising:

responsive to a determination to wake the thread, using the central processing unit identifier to identify the processor on which to wake the thread; and

placing the thread in a run queue for the identified processor.

8. The method of claim 6, further comprising:

loading thread state information using the address of thread state information; and

initiating execution of the thread using the thread state information.

9. A data processing system, comprising:

a plurality of processors;

a wake-and-go mechanism; and

a central repository wake-and-go array,

wherein the wake-and-go mechanism is configured to;

detect a thread running on one of the plurality of processors that is waiting for an event associated with a target address;

populate the central repository wake-and-go storage array with the target address;

responsive to detecting that the thread is waiting for the event, place the thread in a sleep state;

responsive to an event that modifies a data value associated with the target address, determine whether to wake the thread; and

responsive to a determination to wake the thread, place the thread in a non-sleep state.

10. The data processing system of claim 9, wherein detecting a thread that is waiting for an event associated with a target address comprises recognizing a programming idiom that causes the thread to wait for a data value to be written to the target address.

11. The data processing system of claim 9, wherein determining whether to wake the thread comprises determining whether a data value being written to the target address is a data value for which the thread is waiting.

12. The data processing system of claim 9, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

13. The data processing system of claim 9, wherein the central repository wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

14. The data processing system of claim 9, wherein populating the central repository wake-and-go storage array with the target address comprises recording an entry including at least one of a thread identifier, a central processing unit identifier, a target address, an expected data value, a comparison type, a lock bit, a priority value, or an address of thread state information associated with the thread.

15. The data processing system of claim 14, wherein the wake-and-go mechanism is further configured to:

responsive to a determination to wake the thread, use the central processing unit identifier to identify the processor on which to wake the thread; and

place the thread in a run queue for the identified processor.

16. The data processing system of claim 14, wherein the wake-and-go mechanism is further configured to:

load thread state information using the address of thread state information; and

initiate execution of the thread using the thread state information.

17. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

detect a thread running on one of a plurality of processors that is waiting for an event associated with a target address;

populate a central repository wake-and-go storage array with the target address;

responsive to detecting that the thread is waiting for the event, place the thread in a sleep state;

responsive to an event that modifies a data value associated with the target address, determine whether to wake the thread; and

responsive to a determination to wake the thread, place the thread in a non-sleep state.

18. The computer program product of claim 17, wherein populating the central repository wake-and-go storage array with the target address comprises recording an entry including at least one of a thread identifier, a central processing unit identifier, a target address, an expected data value, a comparison type, a lock bit, a priority value, or an address of thread state information associated with the thread.

19. The computer program product of claim 18, wherein the computer readable program further causes the computing device to:

responsive to a determination to wake the thread, use the central processing unit identifier to identify the processor on which to wake the thread; and

place the thread in a run queue for the identified processor.

20. The computer program product of claim 19, wherein the computer readable program further causes the computing device to:

load thread state information using the address of thread state information; and

initiate execution of the thread using the thread state information.