STRAINED CMOS DEVICE, CIRCUIT AND METHOD OF FABRICATION

• US 20110175166A1
• Filed: 01/19/2010
• Published: 07/21/2011
• Est. Priority Date: 01/19/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bedell, Stephen W., Khakifirooz, Ali, Cheng, Kangguo, Shahidi, Ghavam G., Doris, Bruce B., Sadana, Devendra K.
• Granted Patent: US 8,169,025 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

Claims

1. A method for fabricating a semiconductor device, comprising:

providing a strained semiconductor layer having a strain in at least one axis;

forming at least one long fin and at least one short fin in the semiconductor layer such that the at least one long fin has a strained length along the at least one axis;

forming an n-type transistor on the at least one long fin; and

forming a p-type transistor on the at least one short fin.

2. The method as recited in claim 1, wherein forming the at least one long fin includes forming a long fin with a length of about 1 micron.

3. The method as recited in claim 1, wherein forming the at least one long fin includes forming a long fin with a length extending at least about 500 nm from each side of a position location of an n-type transistor.

4. The method as recited in claim 1, wherein forming the at least one short fin includes forming a short fin with a length of at less than 300 nm.

5. The method as recited in claim 1, wherein providing a strained semiconductor layer includes providing a Strained Silicon Directly on Insulator (SSDOI) wafer with biaxial tensile strain.

6. The method as recited in claim 1, further comprising forming gate structures wherein the gate structures maintain strain in the at least one long fin.

7. The method as recited in claim 1, further comprising forming raised source and drain regions wherein the raised source and drain regions maintain strain in the at least one long fin.

8. The method as recited in claim 1, wherein the semiconductor device includes a static random access memory, and the method further comprising forming pull-down (PD) and pass-gate (PG) n-type transistors on long fins, and pull-up (PU) p-type transistors on short fins.

9. The method as recited in claim 1, wherein the at least one long fin includes a strain of at least 1% and the at least one short fin includes a negligible strain.

10. A method for fabricating a semiconductor device, comprising:

providing a providing a Strained Silicon Directly on Insulator (SSDOI) wafer with biaxial tensile strain;

patterning long fins and short fins in a semiconductor layer of the wafer such that the long fin has a strained length along its longitudinal axis, and the short fins having dimensions to substantially remove residual strain;

forming n-type transistors on the long fins including gate structures and raised active area regions such that the gate structures and the raised active area regions provide anchoring to maintain strain in the strain length of the long fins; and

forming p-type transistors on the short fins.

11. The method as recited in claim 10, wherein forming the long fins includes forming a long fin with a length of about 1 micron.

12. The method as recited in claim 10, wherein forming the long fins includes forming a long fin with a length extending at least about 500 nm from each side of a position location of an n-type transistor.

13. The method as recited in claim 10, wherein forming the short fin includes forming a short fin with a length of at less than 300 nm.

14. The method as recited in claim 10, wherein the semiconductor device includes a static random access memory, and the method further comprising forming pull-down (PD) and pass-gate (PG) n-type transistors on long fins, and pull-up (PU) p-type transistors on short fins.

15. The method as recited in claim 10, wherein the long fins include a strain of at least 1%.

16. A semiconductor device, comprising:

a strained semiconductor layer formed into at least one long fin and at least one short fin such that the at least one long fin has a strained length;

an n-type transistor formed on the at least one long fin wherein the strained length improves device operation; and

a p-type transistor formed on the short fin.

17. The device as recited in claim 16, wherein the at least one long fin includes a length of about 1 micron.

18. The device as recited in claim 16, wherein the at least one long fin includes a length extending at least about 500 nm from each side of a position location of an n-type transistor.

19. The device as recited in claim 16, wherein the at least one short fin includes a length of less than 300 nm.

20. The device as recited in claim 16, wherein the strained semiconductor layer includes a Strained Silicon Directly on Insulator (SSDOI) wafer with biaxial tensile strain.

21. The device as recited in claim 16, wherein the n-type transistors include gate structures and the gate structures maintain strain in the at least one long fin.

22. The device as recited in claim 16, wherein the n-type transistors include raised source and drain regions wherein the raised source and drain regions maintain strain in the at least one long fin.

23. The device as recited in claim 16, wherein the semiconductor device includes a static random access memory having pull-down (PD) and pass-gate (PG) n-type transistors on long fins, and pull-up (PU) p-type transistors on short fins.

24. The device as recited in claim 16, wherein the at least one long fin includes a strain of at least 1%.