INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING ENHANCED ELECTROMIGRATION RESISTANCE

• US 20110175226A1
• Filed: 01/21/2010
• Published: 07/21/2011
• Est. Priority Date: 01/21/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lustig, Naftali E., Grunow, Stephan, Wang, Ping-Chuan, Hu, Chao-Kun, Simon, Andrew H., Bonilla, Griselda, Filippi, Ronald G., Chanda, Kaushik
• Granted Patent: US 8,232,646 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line

Claims

1. An interconnect structure for an integrated circuit (IC) device, the structure comprising:

a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein;

wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

2. The structure of claim 1, wherein adjacent vertical diffusion barriers are spaced apart by a distance less than or equal to a Blech length of the metal line.

3. The structure of claim 2, wherein the metal line comprises copper.

4. The structure of claim 1, wherein the liner material of the via corresponding to the one or more vertical diffusion barriers comprises a same material as a liner material for bottom and sidewall surfaces of the metal line.

5. The structure of claim 4, wherein the vertical diffusion barriers comprise one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, manganese, cobalt and combinations thereof.

6. An interconnect structure for an integrated circuit (IC) device, the structure comprising:

a metal line formed within a dielectric layer, the metal line comprising a plurality of individual metal segments separated by vertical diffusion barriers;

wherein the vertical diffusion barriers correspond to a liner material of one or more vias formed above the metal line segments, with each via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line by electrically connecting adjacent metal line segments to one another.

7. The structure of claim 6, wherein the individual metal segments between vertical diffusion barriers have a length less than or equal to a Blech length of the metal line.

8. The structure of claim 7, wherein the metal line segments and the bottom most portions of the one or more vias comprise copper.

9. The structure of claim 6, wherein the liner material of the via corresponding to the one or more vertical diffusion barriers comprises a same material as a liner material for bottom and sidewall surfaces of the metal line.

10. The structure of claim 9, wherein the vertical diffusion barriers comprise one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, manganese, cobalt and combinations thereof.

11. A method of forming an interconnect structure for an integrated circuit (IC) device, the method comprising:

forming a plurality of individual metal line segments within a dielectric layer; and

forming a via over the individual metal line segments, and filling the via with a liner material and a metal fill material such that the liner material on sidewalls of a bottom most portion of the via defines one or more vertical diffusion barriers and the metal fill material in the bottom most portion of the via electrically connects adjacent metal line segments to one another, and thereby defining a metal line.

12. The method of claim 11, wherein the individual metal line segments between vertical diffusion barriers have a length less than or equal to a Blech length of the metal line.

13. The method of claim 12, wherein the metal line segments and the bottom most portions of the one or more vias comprise copper.

14. The method of claim 11, wherein the liner material of the via corresponding to the one or more vertical diffusion barriers comprises a same material as a liner material for bottom and sidewall surfaces of the metal line segments.

15. The method of claim 14, wherein the vertical diffusion barriers comprise one of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, manganese, cobalt and combinations thereof.