BUS DRIVER FOR AVOIDING AN OVERVOLTAGE

• US 20110175592A1
• Filed: 09/30/2008
• Published: 07/21/2011
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Jarrige, Nicolas, Ahmed, Hamada, Huot-Marchand, Alexis, Besse, Patrice
• Granted Patent: US 8,558,520 B2
• Time in Patent Office: Days
• US Class Current: 323/311
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/167 using parallel switching arrangements
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage.

Claims

1. An electrical circuit for manipulating at least one of a voltage and a current on a bus wire, wherein the circuit comprises:

a first switch having a first gate, a first source, and a first potential reduction unit, wherein the manipulating of the at least one of a voltage and a current on the bus wire is controllable by a change of a gate voltage at the first gate, wherein the first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is causable by turning an output of a first control voltage source into an high-impedance state.

2. The electrical circuit as claimed in claim 1, wherein the circuit comprises a second switch having a second gate, a second source, and a second potential reduction unit, wherein the second potential reduction unit is suitable for lowering a potential difference between the second gate and the second source of the second switch, wherein the lowering of the potential difference is caused by a shutting-off of a second control voltage.

3. The electrical circuit as claimed in claim 2, wherein the second potential reduction unit has a higher time constant than the first potential reduction unit.

4. The electrical circuit as claimed in claim 2, wherein the second potential reduction unit comprises the first potential reduction unit.

5. The electrical circuit as claimed in claim 2, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

6. The electrical circuit as claimed in claim 1, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

7. The electrical circuit as claimed in claim 6, wherein at least one of the first and second timing elements comprises a first respectively second capacity.

8. The electrical circuit as claimed in claim 7, wherein at least one of the first and second timing elements comprises a first respectively second RC element.

9. The electrical circuit as claimed in claim 6, wherein at least one of the first and second timing elements comprises a first respectively second current source.

12. The electrical circuit as claimed in claim 3, wherein the second potential reduction unit comprises the first potential reduction unit.

13. The electrical circuit as claimed in claim 3, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

14. The electrical circuit as claimed in claim 4, wherein a resistor of the second potential reduction unit is connected in series with the first potential reduction unit.

15. The electrical circuit as claimed in claim 2, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

16. The electrical circuit as claimed in claim 3, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

17. The electrical circuit as claimed in claim 4, wherein at least one of the first and second potential reduction unit forms at least a portion of a first respectively second timing element.

18. The electrical circuit as claimed in claim 7, wherein at least one of the first and second timing elements comprises a first respectively second current source.

19. The electrical circuit as claimed in claim 7, wherein at least one of the first and second timing elements comprises a first respectively second current source.

10. A method for avoiding an overvoltage on a bus wire, wherein the method comprises:

recognizing an error condition;

breaking a first control circuit of a first gate of a first switch at an interruption moment when the first gate is supplied via the first control circuit with a first control voltage by turning an output of a first control voltage source into an high impedance state; and

lowering a voltage at the first gate with a first time constant.

11. The method as claimed in claim 10, wherein the method further comprises:

breaking a second control circuit of a second gate of a second switch, at the interruption moment when the second gate is supplied via the second control circuit with a second control voltage; and

lowering a voltage at the second gate with a second time constant being higher than the first time constant.