FRACTIONAL-N PHASE-LOCKED LOOP
First Claim
1. A fractional-N phase-locked loop (PLL), comprising:
- a first phase detector configured to compare first phase difference to generate a first error signal indicative of the first phase difference;
a first voltage-controlled oscillator (VCO) configured to generate an output frequency according to the first error signal;
a frequency multiplier configured to perform frequency multiplication on the output frequency to generate a multiplied signal, the frequency multiplier comprising a second phase-locked loop, thereby forming a second loop therein; and
a first frequency divider configured to perform frequency division on the multiplied signal to generate a first divided signal, the first divided signal and a reference frequency being then compared by the first phase detector to determine the first phase difference;
wherein the first phase detector, the first voltage-controlled oscillator, the frequency multiplier and the first frequency divider form a first loop.
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Abstract
A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.
14 Citations
10 Claims
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1. A fractional-N phase-locked loop (PLL), comprising:
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a first phase detector configured to compare first phase difference to generate a first error signal indicative of the first phase difference; a first voltage-controlled oscillator (VCO) configured to generate an output frequency according to the first error signal; a frequency multiplier configured to perform frequency multiplication on the output frequency to generate a multiplied signal, the frequency multiplier comprising a second phase-locked loop, thereby forming a second loop therein; and a first frequency divider configured to perform frequency division on the multiplied signal to generate a first divided signal, the first divided signal and a reference frequency being then compared by the first phase detector to determine the first phase difference; wherein the first phase detector, the first voltage-controlled oscillator, the frequency multiplier and the first frequency divider form a first loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification