SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

• US 20110175670A1
• Filed: 01/12/2011
• Published: 07/21/2011
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SHISHIDO, Hideaki
• Granted Patent: US 8,796,785 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: G02F 1/133305 Flexible substrates, e.g. plastics, organic film
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.

Claims

1. A semiconductor device comprising:

first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;

(n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;

first to n-th signal lines; and

(n+1)-th to m-th signal lines,

wherein a signal is supplied to the first signal line in the first period through the first switch, and the first signal line is in a floating state in the second period,

wherein a signal is supplied to the n-th signal line in the first period through the n-th switch, and the n-th signal line is in a floating state in the second period,

wherein the (n+1)-th signal line is in a floating state in the first period, and a signal is supplied to the (n+1)-th signal line in the second period through the (n+1)-th switch,

wherein the m-th signal line is in a floating state in the first period, and a signal is supplied to the m-th signal line in the second period through the m-th switch,

wherein the first to m-th signal lines are parallel or approximately parallel,

wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−

1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line.

2. The semiconductor device according to claim 1,

wherein a signal is supplied to any one of the first to n-th signal lines and to any one of the (n+1)-th to m-th signal lines through a same wiring.

3. The semiconductor device according to claim 1,

wherein m=2n is satisfied.

4. The semiconductor device according to claim 1,

wherein the first to m-th switches are first to m-th transistors.

5. The semiconductor device according to claim 4,

wherein the first to m-th transistors are spaced at regular intervals or at approximately regular intervals, and channel length directions of the first to m-th transistors are perpendicular or approximately perpendicular to the first to m-th signal lines,

wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,

wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,

wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th signal line, and

wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th signal line.

6. The semiconductor device according to claim 4,

wherein channel, formation regions of the first to m-th transistors comprise an oxide semiconductor.

7. The semiconductor device according to claim 4,

wherein a shift register circuit which controls switching of the first to m-th transistors is included, and

wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

8. The semiconductor device according to claim 1,

wherein an electronic device comprises the semiconductor device.

9. A semiconductor device comprising:

first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;

(n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;

first to n-th source signal lines; and

(n+1)-th to m-th source signal lines,

wherein an image signal is supplied to the first source signal line in the first period through the first switch, and the first source signal line is in a floating state in the second period,

wherein an image signal is supplied to the n-th source signal line in the first period through the n-th switch, and the n-th source signal line is in a floating state in the second period,

wherein the (n+1)-th source signal line is in a floating state in the first period, and a signal is supplied to the (n+1)-th source signal line in the second period through the (n+1)-th switch,

wherein the m-th source signal line is in a floating state in the first period, and a signal is supplied to the m-th source signal line in the second period through the m-th switch,

wherein the first to m-th source signal lines are parallel or approximately parallel,

wherein a distance between the n-th source signal line and the (n+1)-th source signal line is longer than a distance between the (n−

1)-th source signal line and the n-th source signal line and is longer than a distance between the (n+1)-th source signal line and the (n+2)-th source signal line.

10. The semiconductor device according to claim 9,

wherein a signal is supplied to any one of the first to n-th source signal lines and to any one of the (n+1)-th to m-th source signal lines through a same wiring.

11. The semiconductor device according to claim 9,

wherein m=2n is satisfied.

12. The semiconductor device according to claim 9,

wherein the first to m-th switches are first to m-th transistors.

13. The semiconductor device according to claim 12,

wherein the first to m-th transistors are spaced at regular intervals or at approximately regular intervals, and channel length directions of the first to m-th transistors are perpendicular or approximately perpendicular to the first to m-th source signal lines,

wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,

wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,

wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th source signal line, and

wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th source signal line.

14. The semiconductor device according to claim 12,

wherein channel formation regions of the first to m-th transistors comprise an oxide semiconductor.

15. The semiconductor device according to claim 12,

wherein a shift register circuit which controls switching of the first to m-th transistors is included, and

wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

16. The semiconductor device according to claim 9,

wherein a pixel electrically connected to any one of the first to m-th source signal lines is included, and

wherein the pixel includes a transistor whose channel formation region comprises an oxide semiconductor.

17. The semiconductor device according to claim 16,

wherein a gate signal line driver circuit which controls switching of the transistor included in the pixel is included, and

wherein the gate signal line driver circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

18. The semiconductor device according to claim 9,

wherein an electronic device comprises the semiconductor device.

19. A semiconductor device comprising:

first to n-th switches (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;

(n+1)-th to m-th switches (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;

first to n-th signal lines; and

(n+1)-th to m-th signal lines,

wherein the first to m-th signal lines are parallel or approximately parallel,

wherein a distance between the n-th signal line and the (n+1)-th signal line is longer than a distance between the (n−

1)-th signal line and the n-th signal line and is longer than a distance between the (n+1)-th signal line and the (n+2)-th signal line.

20. The semiconductor device according to claim 19,

wherein a signal is supplied to any one of the first to n-th signal lines and to any one of the (n+1)-th to m-th signal lines through a same wiring.

21. The semiconductor device according to claim 19,

wherein m=2n is satisfied.

22. The semiconductor device according to claim 19,

wherein the first to m-th switches are first to m-th transistors.

23. The semiconductor device according to claim 22,

wherein the first to m-th transistors are spaced at regular intervals or at approximately regular intervals, and channel length directions of the first to m-th transistors are perpendicular or approximately perpendicular to the first to m-th signal lines,

wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,

wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,

wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th signal line, and

wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th signal line.

24. The semiconductor device according to claim 22,

wherein channel formation regions of the first to m-th transistors comprise an oxide semiconductor.

25. The semiconductor device according to claim 22,

wherein a shift register circuit which controls switching of the first to m-th transistors is included, and

wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

26. The semiconductor device according to claim 19,

wherein an electronic device comprises the semiconductor device.

27. A semiconductor device comprising:

first to n-th transistors (n is a natural number of 2 or more) configured to be turned on in a first period and turned off in a second period;

(n+1)-th to m-th transistors (m is a natural number of n+2 or more) configured to be turned off in the first period and turned on in the second period;

first to n-th source signal lines; and

(n+1)-th to m-th source signal lines,

wherein the first to m-th source signal lines are parallel or approximately parallel,

wherein one of a source terminal and a drain terminal of the n-th transistor is closer to the (n+1)-th transistor than the other of the source terminal and the drain terminal of the n-th transistor,

wherein one of a source terminal and a drain terminal of the (n+1)-th transistor is closer to the n-th transistor than the other of the source terminal and the drain terminal of the (n+1)-th transistor,

wherein the other of the source terminal and the drain terminal of the n-th transistor is electrically connected to the n-th source signal line, and

wherein the other of the source terminal and the drain terminal of the (n+1)-th transistor is electrically connected to the (n+1)-th source signal line.

28. The semiconductor device according to claim 27,

wherein a signal is supplied to any one of the first to n-th source signal lines and to any one of the (n+1)-th to m-th source signal lines through a same wiring.

29. The semiconductor device according to claim 27,

wherein m=2n is satisfied.

30. The semiconductor device according to claim 27,

wherein the first to m-th transistors are spaced at regular intervals or at approximately regular intervals, and channel length directions of the first to m-th transistors are perpendicular or approximately perpendicular to the first to m-th source signal lines.

31. The semiconductor device according to claim 27,

wherein channel formation regions of the first to m-th transistors comprise an oxide semiconductor.

32. The semiconductor device according to claim 27,

wherein a shift register circuit which controls switching of the first to m-th transistors is included, and

wherein the shift register circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

33. The semiconductor device according to claim 27,

wherein a pixel electrically connected to any one of the first to m-th source signal lines is included, and

wherein the pixel includes a transistor whose channel formation region comprises an oxide semiconductor.

34. The semiconductor device according to claim 33,

wherein a gate signal line driver circuit which controls switching of the transistor included in the pixel is included, and

wherein the gate signal line driver circuit includes a transistor whose channel formation region comprises an oxide semiconductor.

35. The semiconductor device according to claim 27,

wherein an electronic device comprises the semiconductor device.