SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

• US 20110176355A1
• Filed: 01/12/2011
• Published: 07/21/2011
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yakubo, Yuto, Ieda, Yoshinori, Furutani, Kazuma, Yamazaki, Shunpei, Kato, Kiyoshi
• Granted Patent: US 8,780,629 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.

Claims

1. A semiconductor device comprising:

a non-volatile memory cell including a first transistor, a second transistor, and a capacitor,

wherein a first semiconductor material included in the first transistor is different from a second semiconductor material included in the second transistor,

wherein the first semiconductor material is an oxide semiconductor,

wherein one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, and

wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁴ seconds without power supply.

2. The semiconductor device according to claim 1, wherein off-state current of the first transistor is lower than off-state current of the second transistor.

3. The semiconductor device according to claim 1, wherein a switching speed of the second transistor is higher than a switching speed of the first transistor.

4. The semiconductor device according to claim 1, wherein the first semiconductor material is a material having an energy gap larger than 3 eV.

5. The semiconductor device according to claim 1, wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁶ seconds without power supply.

6. A driving method of a semiconductor device comprising a non-volatile memory cell including a first transistor, a second transistor, and a capacitor,

wherein a first semiconductor material included in the first transistor is different from a second semiconductor material included in the second transistor,

wherein the first semiconductor material is an oxide semiconductor, and

wherein one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor,

the driving method comprising the steps of:

in a first write period, applying a first potential to the gate of the second transistor and the capacitor through the first transistor, whereby first charge is held in the capacitor and the gate of the second transistor; and

in a second write period, applying a second potential to the gate of the second transistor and the capacitor which are holding the first charge through the first transistor, whereby second charge is held in the capacitor and the gate of the second transistor, without an erasing operation between the first write period and the second write period.

7. The driving method of a semiconductor device according to claim 6, wherein off-state current of the first transistor is lower than off-state current of the second transistor.

8. The driving method of a semiconductor device according to claim 6, wherein a switching speed of the second transistor is higher than a switching speed of the first transistor.

9. The driving method of a semiconductor device according to claim 6, wherein the first semiconductor material is a material having an energy gap larger than 3 eV.

10. The driving method of a semiconductor device according to claim 6, wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁴ seconds without power supply.

11. The driving method of a semiconductor device according to claim 6, wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁶ seconds without power supply.

12. A driving method of a semiconductor device comprising a non-volatile memory cell including a first transistor, a second transistor, and a capacitor,

wherein a first semiconductor material included in the first transistor is different from a second semiconductor material included in the second transistor,

wherein the first semiconductor material is an oxide semiconductor, and

wherein one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor,

the driving method comprising the steps of:

in a first write period, applying a first potential to the gate of the second transistor and the capacitor through the first transistor by turning on the first transistor, whereby first charge is held in the capacitor and the gate of the second transistor by turning off the first transistor; and

in a second write period, applying a second potential to the gate of the second transistor and the capacitor which are holding the first charge through the first transistor by turning on the first transistor, whereby second charge is held in the capacitor and the gate of the second transistor by turning off the first transistor, without an erasing operation between the first write period and the second write period.

13. The driving method of a semiconductor device according to claim 12, wherein off-state current of the first transistor is lower than off-state current of the second transistor.

14. The driving method of a semiconductor device according to claim 12, wherein a switching speed of the second transistor is higher than a switching speed of the first transistor.

15. The driving method of a semiconductor device according to claim 12, wherein the first semiconductor material is a material having an energy gap larger than 3 eV.

16. The driving method of a semiconductor device according to claim 12, wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁴ seconds without power supply.

17. The driving method of a semiconductor device according to claim 12, wherein the non-volatile memory cell is configured to hold data for at least longer than or equal to 1×

10⁶ seconds without power supply.