SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME

• US 20110176357A1
• Filed: 01/18/2011
• Published: 07/21/2011
• Est. Priority Date: 01/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Granted Patent: US 8,593,856 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

It is an object to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed and a signal processing circuit including the memory device. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. The memory element is applied to a memory device such as a register or a cache memory included in a signal processing circuit.

Claims

1. A signal processing circuit comprising:

an arithmetic circuit; and

a first memory device configured to store data from the arithmetic circuit,

wherein the first memory device comprises a first plurality of memory elements, and

wherein each of the first plurality of memory elements comprises a first pair of phase-inversion elements configured to hold the data by connection of an output terminal of one of the first pair of phase-inversion elements to an input terminal of the other of the first pair of phase-inversion elements and an output terminal of the other of the first pair of phase-inversion elements to an input terminal of the one of the first pair of phase-inversion elements, a first capacitor, and a first transistor which includes a first oxide semiconductor in a first channel formation region and is configured to control writing of the data to the first capacitor.

2. The signal processing circuit according to claim 1, wherein off-state current density of the first transistor is less than or equal to 100 zA/μ

m.

3. The signal processing circuit according to claim 1, wherein each of the first pair of phase-inversion elements is an inverter or a clocked inverter.

4. The signal processing circuit according to claim 1, wherein the first oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

5. The signal processing circuit according to claim 1, wherein a hydrogen concentration of the first channel formation region is less than or equal to 5×

10¹⁹/cm³.

6. The signal processing circuit according to claim 1, wherein the signal processing circuit is selected from the group consisting of an LSI comprising a CPU, a DSP and a microcontroller.

7. The signal processing circuit according to claim 1, further comprising a second memory device configured to store data from the arithmetic circuit,

wherein the second memory device comprises a second plurality of memory elements, and

wherein each of the second plurality of memory elements comprises a second pair of phase-inversion elements configured to hold the data by connection of an output terminal of one of the second pair of phase-inversion elements to an input terminal of the other of the second pair of phase-inversion elements and an output terminal of the other of the second pair of phase-inversion elements to an input terminal of the one of the second pair of phase-inversion elements, a second capacitor, and a second transistor which includes a second oxide semiconductor in a second channel formation region and is configured to control writing of the data to the second capacitor.

8. The signal processing circuit according to claim 7,

wherein the first memory device further comprises a first switching element configured to control supply of power supply voltage to the first plurality of memory elements, and

wherein the second memory device further comprises a second switching element configured to control supply of power supply voltage to the second plurality of memory elements.

9. A signal processing circuit comprising:

a plurality of arithmetic circuits; and

a plurality of memory devices configured to store data from the plurality of arithmetic circuits,

wherein each of the plurality of arithmetic circuits includes a logic circuit configured to carry out arithmetic processing and a first switching element configured to control supply of power supply voltage to the logic circuit,

wherein each of the plurality of memory devices includes a plurality of memory elements and a second switching element configured to control supply of power supply voltage to the plurality of memory elements, and

wherein each of the plurality of memory elements includes a pair of phase-inversion elements configured to hold the data by connection of an output terminal of one phase-inversion element to an input terminal of the other phase-inversion element and an output terminal of the other phase-inversion element to an input terminal of the one phase-inversion element, a capacitor, and a transistor which includes an oxide semiconductor in a channel formation region and is configured to control writing of the data to the capacitor.

10. The signal processing circuit according to claim 9, wherein off-state current density of the transistor is less than or equal to 100 zA/μ

m.

11. The signal processing circuit according to claim 9, wherein each of the pair of phase-inversion elements is an inverter or a clocked inverter.

12. The signal processing circuit according to claim 9, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

13. The signal processing circuit according to claim 9, wherein a hydrogen concentration of the channel formation region is less than or equal to 5×

10¹⁹/cm³.

14. The signal processing circuit according to claim 9, wherein the signal processing circuit is selected from the group consisting of an LSI comprising a CPU, a DSP and a microcontroller.

15. A semiconductor device comprising:

a memory element comprising a first phase-inversion element, a second phase-inversion element, a capacitor and a first transistor,

wherein an input terminal of the first phase-inversion element is electrically connected to an output terminal of the second phase-inversion element,

wherein an input terminal of the second phase-inversion element is electrically connected to an output terminal of the first phase-inversion element,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,

wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the first phase-inversion element, and

wherein the first transistor comprises an oxide semiconductor in a channel formation region.

16. The semiconductor device according to claim 15, further comprising a second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the input terminal of the first phase-inversion element, and

wherein the other of the source and the drain of the second transistor is electrically connected to the output terminal of the second phase-inversion element.

17. The semiconductor device according to claim 15, further comprising an arithmetic circuit,

wherein the memory element is configured to store data from the arithmetic circuit.

18. The semiconductor device according to claim 15, wherein off-state current density of the first transistor is less than or equal to 100 zA/μ

m.

19. The semiconductor device according to claim 15, wherein each of the first phase-inversion element and the second phase-inversion element is an inverter or a clocked inverter.

20. The semiconductor device according to claim 15, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

21. The semiconductor device according to claim 15, wherein a hydrogen concentration of the channel formation region is less than or equal to 5×

10¹⁹ cm³.

22. The semiconductor device according to claim 15, wherein the signal processing circuit is selected from the group consisting of an LSI comprising a CPU, a DSP and a microcontroller.

23. A method for driving a signal processing circuit comprising:

an arithmetic circuit; and

a memory device configured to store data from the arithmetic circuit,

wherein the memory device comprises a memory element, and

wherein the memory element comprises a pair of phase-inversion elements configured to hold the data by connection of an output terminal of one phase-inversion element to an input terminal of the other phase-inversion element and an output terminal of the other phase-inversion element to all input terminal of the one phase-inversion element, a capacitor, and a transistor which includes a oxide semiconductor in a channel formation region and is configured to control writing of the data to the capacitor,

the method comprising the steps of;

writing data from the arithmetic circuit into the memory element;

writing data into the capacitor by turning on the transistor;

turning off the transistor after the writing data into the capacitor; and

stopping supply of power supply voltage to the arithmetic circuit and the memory device.

24. A method for driving a signal processing circuit comprising:

a plurality of arithmetic circuits; and

a memory device configured to store data from the plurality of arithmetic circuits,

wherein the memory device comprises a memory element, and

wherein the memory element comprises a pair of phase-inversion elements configured to hold the data by connection of an output terminal of one phase-inversion element to an input terminal of the other phase-inversion element and an output terminal of the other phase-inversion element to an input terminal of the one phase-inversion element, a capacitor, and a transistor which includes a oxide semiconductor in a channel formation region and is configured to control writing of the data to the capacitor,

the method comprising the steps of;

writing data from one arithmetic circuit of the plurality of arithmetic circuits into the memory element;

writing data into the capacitor by turning on the transistor;

turning off the transistor after the writing data into the capacitor; and

stopping supply of power supply voltage to the one arithmetic circuit and the memory device.