SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device comprising:
- a memory cell array comprising memory cells arranged in matrix, the memory cell array including a main memory region and a redundant memory region;
a driver circuit configured to drive the memory cell array; and
a memory controller configured to control operation of the driver circuit,wherein the memory controller comprises;
a memory portion configured to store address data of a defective memory cell in the main memory region; and
a redundant address storage portion configured to store address data of the redundant memory region.
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Accused Products
Abstract
A driver circuit having a redundant control function to store address data of a defective memory cell is provided to compensate a defect of a memory cell array. In other words, address data of a defective memory cell is stored not by using part of the memory cell array, but by using a non-volatile memory, which is provided in a memory controller, to store address data of a defective memory cell. The memory controller storing the address data of a defective memory cell contributes an increase in process speed, because it is not necessary to access the memory cell array in order to obtain the address data of the defective memory cell.
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Citations
18 Claims
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1. A semiconductor memory device comprising:
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a memory cell array comprising memory cells arranged in matrix, the memory cell array including a main memory region and a redundant memory region; a driver circuit configured to drive the memory cell array; and a memory controller configured to control operation of the driver circuit, wherein the memory controller comprises; a memory portion configured to store address data of a defective memory cell in the main memory region; and a redundant address storage portion configured to store address data of the redundant memory region. - View Dependent Claims (2, 3, 4)
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5. A semiconductor memory device comprising:
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a memory cell array comprising memory cells arranged in matrix, the memory cell array including a main memory region and a redundant memory region; a driver circuit configured to drive the memory cell array; and a memory controller configured to control operation of the driver circuit, wherein the memory controller comprises; a memory portion configured to store address data of a defective memory cell in the main memory region; and a redundant address storage portion configured to store address data of the redundant memory region, wherein the memory portion comprises a memory cell, and the memory cell comprises a first transistor, a second transistor and a capacitor, and wherein a gate electrode of the first transistor, a drain electrode of the second transistor and an electrode of the capacitor are electrically connected to one another. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device comprising:
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a memory cell array comprising memory cells arranged in matrix, the memory cell array including a main memory region and a redundant memory region; a driver circuit configured to drive the memory cell array; and a memory controller configured to control operation of the driver circuit, wherein each of the memory cells comprises a first transistor, a second transistor and a first capacitor, wherein a gate electrode of the first transistor, a drain electrode of the second transistor and an electrode of the first capacitor are electrically connected to one another, wherein the memory controller comprises; a memory portion configured to store address data of a defective memory cell in the main memory region; and a redundant address storage portion configured to store address data of the redundant memory region, wherein the memory portion comprises a memory cell, and the memory cell comprises a third transistor, a fourth transistor and a second capacitor, and wherein a gate electrode of the third transistor, a drain electrode of the fourth transistor and an electrode of the second capacitor are electrically connected to one another. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification