SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

• US 20110176652A1
• Filed: 01/04/2011
• Published: 07/21/2011
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUROKAWA, Yoshiyuki
• Granted Patent: US 9,871,526 B2
• Time in Patent Office: Days
• US Class Current: 377/49
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H03K 23/548 Reversible counters
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected.

Claims

1. A semiconductor device comprising:

an analog/digital converter including an oscillation circuit and a counter circuit, wherein the counter circuit is configured to perform addition or subtraction;

a photo sensor electrically connected to the oscillation circuit, to input a first signal to the oscillation circuit; and

a signal line electrically connected to the counter circuit, to select the addition or the subtraction of the counter circuit,

wherein the oscillation circuit is configured to output a second signal obtained by converting the first signal to the counter circuit, the second signal having an oscillation frequency in accordance with the first signal, and

wherein the counter circuit is configured to perform the addition or the subtraction by using the second signal as a clock signal.

2. The semiconductor device according to claim 1,

wherein the photo sensor includes a photodiode, and

wherein the photodiode is one of a pin photodiode including silicon and a pn photodiode including silicon.

3. The semiconductor device according to claim 1,

wherein the counter circuit is configured to correct a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a second state, using a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a first state,

wherein the counter circuit is configured to subtract the count value when the photo sensor is in the first state, and

wherein the counter circuit is configured to add the count value when the photo sensor is in the second state.

4. The semiconductor device according to claim 1,

wherein the first signal is an analog signal, and

wherein the second signal is a digital signal.

5. The semiconductor device according to claim 1, further comprising:

a readout circuit, the readout circuit including;

a transistor; and

a capacitor electrically connected to the transistor,

wherein the third wiring is electrically connected to the transistor and the capacitor.

6. A semiconductor device comprising:

an analog/digital converter including an oscillation circuit and a counter circuit, wherein the counter circuit is configured to perform addition or subtraction;

a photo sensor including a photodiode, a first transistor, and a second transistor; and

a signal line electrically connected to the counter circuit, to select the addition or the subtraction of the counter circuit,

wherein a first terminal of the photodiode is electrically connected to a first wiring,

wherein a second terminal of the photodiode is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to output a first signal,

wherein a gate of the second transistor is electrically connected to a fourth wiring,

wherein the fourth wiring is electrically connected to the oscillation circuit, to input the first signal to the oscillation circuit,

wherein the oscillation circuit is configured to output a second signal obtained by converting the first signal to the counter circuit, the second signal having an oscillation frequency in accordance with the first signal, and

wherein the counter circuit is configured to perform the addition or the subtraction by using the second signal as a clock signal.

7. The semiconductor device according to claim 6, further comprising a third transistor between the second terminal of the photodiode and the gate of the first transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the second terminal of the photodiode,

wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and

wherein a gate of the third transistor is electrically connected to a fifth wiring.

8. The semiconductor device according to claim 7,

wherein the first transistor and the second transistor include a first layer including crystalline silicon, and

wherein the third transistor includes a second layer including oxide semiconductor.

9. The semiconductor device according to claim 8, wherein the second layer has a carrier concentration lower than 1×

10¹⁴/cm³.

10. The semiconductor device according to claim 6, wherein at least one of the first transistor and the second transistor includes a layer including oxide semiconductor.

11. The semiconductor device according to claim 6, wherein the photodiode is one of a pin photodiode including silicon and a pn photodiode including silicon.

12. The semiconductor device according to claim 6,

wherein the counter circuit is configured to correct a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a second state, using a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a first state,

wherein the counter circuit is configured to subtract the count value when the photo sensor is in the first state, and

wherein the counter circuit is configured to add the count value when the photo sensor is in the second state.

13. The semiconductor device according to claim 6,

wherein the first signal is an analog signal, and

wherein the second signal is a digital signal.

14. The semiconductor device according to claim 6,

wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity,

wherein the second transistor includes a gate electrode, and

wherein the gate electrode overlaps with one of the first region and the second region.

15. The semiconductor device according to claim 6,

wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity, and

wherein the first region and the second region are over and in contact with a same surface.

16. The semiconductor device according to claim 6, further comprising:

a readout circuit, the readout circuit including;

a third transistor; and

a capacitor electrically connected to the third transistor,

wherein the third wiring is electrically connected to the third transistor and the capacitor.

17. A semiconductor device comprising:

an analog/digital converter including an oscillation circuit and a counter circuit, wherein the counter circuit is configured to perform addition or subtraction;

a pixel portion including a photo sensor, the photo sensor including a photodiode, a first transistor, and a second transistor; and

a signal line electrically connected to the counter circuit, to select the addition or the subtraction of the counter circuit,

wherein a first terminal of the photodiode is electrically connected to a first wiring,

wherein a second terminal of the photodiode is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the first transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring configured to output a first signal,

wherein a gate of the second transistor is electrically connected to a fourth wiring,

wherein the fourth wiring is electrically connected to the oscillation circuit, to input the first signal to the oscillation circuit,

wherein the oscillation circuit is configured to output a second signal obtained by converting the first signal to the counter circuit, the second signal having an oscillation frequency in accordance with the first signal, and

wherein the counter circuit is configured to perform the addition or the subtraction by using the second signal as a clock signal.

18. The semiconductor device according to claim 17, further comprising a third transistor between the second terminal of the photodiode and the gate of the first transistor,

wherein one of a source and a drain of the third transistor is electrically connected to the second terminal of the photodiode,

wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, and

wherein a gate of the third transistor is electrically connected to a fifth wiring.

19. The semiconductor device according to claim 18,

wherein the first transistor and the second transistor include a first layer including crystalline silicon, and

wherein the third transistor includes a second layer including oxide semiconductor.

20. The semiconductor device according to claim 19, wherein the second layer has a carrier concentration lower than 1×

10¹⁴/cm³.

21. The semiconductor device according to claim 17, wherein at least one of the first transistor and the second transistor includes a layer including oxide semiconductor.

22. The semiconductor device according to claim 17, wherein the photodiode is one of a pin photodiode including silicon and a pn photodiode including silicon.

23. The semiconductor device according to claim 17,

wherein the counter circuit is configured to correct a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a second state, using a count value calculated in the counter circuit from an electric signal generated by the photo sensor when the photo sensor is in a first state,

wherein the counter circuit is configured to subtract the count value when the photo sensor is in the first state, and

wherein the counter circuit is configured to add the count value when the photo sensor is in the second state.

24. The semiconductor device according to claim 17,

wherein the first signal is an analog signal, and

wherein the second signal is a digital signal.

25. The semiconductor device according to claim 17,

wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity,

wherein the second transistor includes a gate electrode, and

wherein the gate electrode overlaps with one of the first region and the second region.

26. The semiconductor device according to claim 17,

wherein the photodiode includes a first region having n-type conductivity and a second region having a p-type conductivity, and

wherein the first region and the second region are over and in contact with a same surface.

27. The semiconductor device according to claim 17, further comprising:

a readout circuit, the readout circuit including;

a third transistor; and

a capacitor electrically connected to the third transistor,

wherein the third wiring is electrically connected to the third transistor and the capacitor.